LMK5C33414A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70419 Mbytes 页数：99 Pages

TI

德州仪器

LMK5B12212 1-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF) – 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF – 42fs typical/ 60fs maximum RMS jitter at 312.5MHz – 47fs typical/ 65fs maximum RMS jitt

文件：5.65494 Mbytes 页数：97 Pages

TI

德州仪器

LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

文件：4.86813 Mbytes 页数：107 Pages

TI

德州仪器

丝印：LK5C33414A；Package：VQFN；LMK5C33414A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70419 Mbytes 页数：99 Pages

TI

德州仪器

丝印：LK5C33414A-S1；Package：VQFN；LMK5C33414AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70881 Mbytes 页数：99 Pages

TI

德州仪器

丝印：LK5C33414A；Package：VQFN；LMK5C33414A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70419 Mbytes 页数：99 Pages

TI

德州仪器

丝印：LK5C33414A-S1；Package：VQFN；LMK5C33414AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70881 Mbytes 页数：99 Pages

TI

德州仪器

LMK5C33414AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.70881 Mbytes 页数：99 Pages

TI

德州仪器

LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

文件：4.86813 Mbytes 页数：107 Pages

TI

德州仪器

具有 JESD204B/C 和 BAW VCO 的三 DPLL、三 APLL、四输入和 14 输出网络同步器

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.\n\nThe network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmab Ultra-low jitter BAW VCO based Wireless clocks \n \n42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz\n \n47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz\n \n\n \n Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) \n \nProgrammable DPLL;

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德州仪器