LMK5C33414A中文资料德州仪器数据手册PDF规格书

1 Features

• Ultra-low jitter BAW VCO based Wireless clocks

– 42-fs typical/ 60-fs maximum RMS jitter at

491.52 MHz

– 47-fs typical/ 65-fs maximum RMS jitter at

245.76 MHz

• Three high-performance Digital Phase Locked

Loops (DPLLs) with paired Analog Phase Locked

Loops (APLLs)

– Programmable DPLL loop bandwidth from 1

mHz to 4 kHz

– < 1-ppt DCO frequency adjustment step size

• Four differential or single-ended DPLL inputs

– 1-Hz (1-PPS) to 800-MHz input frequency

– Digital holdover and hitless switching

• 14 differential outputs with programmable HSDS/

LVPECL, LVDS and HSCL output formats

– Up to 18 total frequency outputs when

configured with 6 LVCMOS frequency outputs

on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2

and 12 differential outputs

– 1-Hz (1-PPS) to 1250-MHz output frequency

with programmable swing and common mode

– PCIe Gen 1 to 6 compliant

• I2C, 3-wire SPI, or 4-wire SPI interface

• Ambient operating temperature: –40°C to 85°C

2 Applications

• 4G and 5G Wireless Networks

– Active Antenna System (AAS), mMIMO

– Macro Remote Radio Unit (RRU)

– CPRI/eCPRI Baseband, Centralized,

Distributed Units (BBU, CU, DU)

– Small cell base station

• SyncE (G.8262), SONET/SDH (Stratum 3/3E,

G.813, GR-1244, GR-253), IEEE 1588 PTP

secondary clock

• Jitter cleaning, wander attenuation and reference

clock generation for 56G/112G PAM-4 SerDes

• Optical Transport Networks (OTN G.709)

• Broadband fixed line access

• Industrial

– Test and measurement

3 Description

The LMK5C33414A is a high-performance network

synchronizer and jitter cleaner designed to meet the

stringent requirements of wireless communications

and infrastructure applications.

The network synchronizer integrates three DPLLs to

provide hitless switching and jitter attenuation with

programmable loop bandwidth and no external loop

filters, maximizing flexibility and ease of use. Each

DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI's

proprietary Bulk Acoustic Wave (BAW) technology

and can generate 491.52-MHz output clocks with

42-fs typical / 60-fs maximum RMS jitter irrespective

of the DPLL reference input frequency and jitter

characteristics. APLL2 and APLL1 provide options for

a second or third frequency and/or synchronization

domain.

Reference validation circuitry monitors the DPLL

reference clocks and performs a hitless switch

between them upon detecting a switchover event.

Zero-Delay Mode (ZDM) and phase cancellation may

be enabled to control the phase relationship from

input to outputs.

The device is fully programmable through I2C or SPI

interface. The onboard EEPROM can be used to

customize system start-up clocks. The device also

features factory default ROM profiles as fallback

options.