丝印：LMK04102；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04102；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04102；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04102；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04110；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04110；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input

文件：1.52898 Mbytes 页数：15 Pages

TI

德州仪器

Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator

文件：859.06 Kbytes 页数：19 Pages

TI

德州仪器

Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator

文件：859.06 Kbytes 页数：19 Pages

TI

德州仪器

Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input

文件：1.52898 Mbytes 页数：15 Pages

TI

德州仪器