型号：ESD05V14T-LK；Package：SOT-143；Transient Voltage Suppressors for ESD Protection

Feature 450 and 588 Watts Peak Pulse Power per Line (tp=8/20μs) Protects two I/O lines Low clamping voltage Working voltages:5V and 12V Low leakage current IEC61000-4-2 (ESD) ±30kV (air), ±30kV (contact): IEC61000-4-4 (EFT) 40A (5/50ηs) Applications USB Power & Data Line Protection Et

文件：2.39004 Mbytes 页数：4 Pages

UNSEMI

优恩半导体

型号：SR05W；Package：SOT-143；LOW CAPACITANCE TVS DIODE ARRAY

文件：548.98 Kbytes 页数：7 Pages

LEIDITECH

雷卯电子

型号：LMK5C22212ARGCR；Package：VQFN；LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.59617 Mbytes 页数：104 Pages

TI

德州仪器

型号：LMK5C22212ARGCRS1；Package：VQFN；LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.47265 Mbytes 页数：102 Pages

TI1

德州仪器

型号：LMK5C22212ARGCT；Package：VQFN；LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.59617 Mbytes 页数：104 Pages

TI

德州仪器

型号：LMK5C22212ARGCTS1；Package：VQFN；LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.47265 Mbytes 页数：102 Pages

TI1

德州仪器

型号：LMK5C33216ARGCR；Package：VQFN；LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.6477 Mbytes 页数：99 Pages

TI1

德州仪器

型号：LMK5C33216ARGCRS1；Package：VQFN；LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.65279 Mbytes 页数：99 Pages

TI1

德州仪器

型号：LMK5C33216ARGCT；Package：VQFN；LMK5C33216A Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.6477 Mbytes 页数：99 Pages

TI1

德州仪器

型号：LMK5C33216ARGCTS1；Package：VQFN；LMK5C33216AS1 Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless clocks – 42-fs typical/ 60-fs maximum RMS jitter at 491.52 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 245.76 MHz • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs) – Programma

文件：4.65279 Mbytes 页数：99 Pages

TI1

德州仪器