丝印：LK5C22212A；Package：VQFN；LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.59617 Mbytes 页数：104 Pages

TI

德州仪器

丝印：LK5C22212A-S1；Package：VQFN；LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.47265 Mbytes 页数：102 Pages

TI

德州仪器

LMK5C23208A 2-DPLL 3-APLL 2-IN 8-OUT Network Synchronizer With JED204B/ JED204C and BAW VCO for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loop (DPLL) with 3 Analog Phase Locked Loops (APLLs)

文件：4.86813 Mbytes 页数：107 Pages

TI

德州仪器

LMK5B12212 1-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications

1 Features • Ultra-low jitter BAW VCO based Ethernet clocks – 13fs typical RMS jitter at 625MHz with 4MHz 1st order high-pass filter (HPF) – 24fs typical RMS jitter at 312.5MHz with 4MHz 1st order HPF – 42fs typical/ 60fs maximum RMS jitter at 312.5MHz – 47fs typical/ 65fs maximum RMS jitt

文件：5.65494 Mbytes 页数：97 Pages

TI

德州仪器

LMK5C22212A 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With JESD204B/C and BAW for Wireless Communications

1 Features • Ultra-low jitter BAW VCO based Wireless Infrastructure and Ethernet clocks – 40fs typical/ 57fs maximum RMS jitter at 491.52MHz – 50fs typical/ 62fs maximum RMS jitter at 245.76MHz • 2 high-performance Digital Phase Locked Loops (DPLLs) with 2 Analog Phase Locked Loops (APLLs

文件：4.59617 Mbytes 页数：104 Pages

TI

德州仪器