LMK5C22212A中文资料德州仪器数据手册PDF规格书

1 Features

• Ultra-low jitter BAW VCO based Wireless

Infrastructure and Ethernet clocks

– 40fs typical/ 57fs maximum RMS jitter at

491.52MHz

– 50fs typical/ 62fs maximum RMS jitter at

245.76MHz

• 2 high-performance Digital Phase Locked Loop

(DPLL) with 3 Analog Phase Locked Loops

(APLLs)

– Programmable DPLL loop filter bandwidth from

1mHz to 4kHz

– < 1ppt DCO frequency adjustment step size

• 2 differential or single-ended DPLL inputs

– 1Hz (1PPS) to 800MHz input frequency

– Digital Holdover and Hitless Switching

• 8 differential outputs with programmable HSDS,

AC-LVPECL, LVDS and HSCL formats

– Up to 12 total frequency outputs when

configured with 6 LVCMOS frequency outputs

on OUT0_P/N, OUT1_P/N, GPIO1, and GPIO2

and 6 differential outputs on OUT3_P/N to

OUT15_P/N

– 1Hz (1PPS) to 1250MHz output frequency with

programmable swing and common mode

– PCIe Gen 1 to 6 compliant

• I2C or 3-wire/4-wire SPI

2 Applications

• 4G and 5G Wireless Networks

– Active Antenna System (AAS), mMIMO

– Macro Remote Radio Unit (RRU)

– CPRI/eCPRI Baseband, Centralized,

Distributed Units (BBU, CU, DU)

– Small cell base station

• SyncE (G.8262), SONET/SDH (Stratum 3/3E,

G.813, GR-1244, GR-253), IEEE-1588 PTP

secondary clock

• Jitter cleaning, wander attenuation, and reference

clock generation for 112G/224G PAM4 SerDes

• Optical Transport Networks (OTN G.709)

• Broadband fixed line access

• Industrial

– Test and measurement

3 Description

The LMK5C23208A is a high-performance network

synchronizer and jitter cleaner designed to meet the

stringent requirements of wireless communications

and infrastructure applications.

The device integrates two DPLLs and three APLLs

to provide hitless switching and jitter attenuation

with programmable loop bandwidth (LBW) and one

external loop filter capacitor, maximizing flexibility and

ease of use.

APLL3 features an ultra-high performance PLL

with TI's proprietary Bulk Acoustic Wave (BAW)

technology. The BAW APLL can generate 491.52MHz

output clocks with 40fs typical / 60fs maximum RMS

jitter (12kHz to 20MHz) irrespective of the DPLL

reference input frequency and jitter characteristics.

APLL2 and APLL1 (conventional LC VCOs) provide

options for a second or third frequency and/or

synchronization domain.

Reference validation circuitry monitors the DPLL

reference inputs and automatically performs a hitless

switch when the inputs are detected or lost. Zero-

Delay Mode (ZDM) provides control over the phase

relationship between inputs and outputs.

The device is fully programmable through I2C or SPI.

The integrated EEPROM can be used to customize

system start-up clocks. The device also features

factory default ROM profiles as fallback options.