LMK5C22212ARGCR中文资料德州仪器数据手册PDF规格书

1 Features

• Ultra-low jitter BAW VCO based Wireless

Infrastructure and Ethernet clocks

– 40fs typical/ 57fs maximum RMS jitter at

491.52MHz

– 50fs typical/ 62fs maximum RMS jitter at

245.76MHz

• 2 high-performance Digital Phase Locked Loops

(DPLLs) with 2 Analog Phase Locked Loops

(APLLs)

– Programmable DPLL loop filter bandwidth from

1mHz to 4kHz

– < 1ppt DCO frequency adjustment step size

• 2 differential or single-ended DPLL inputs

– 1Hz (1PPS) to 800MHz input frequency

– Digital Holdover and Hitless Switching

• 12 differential outputs with programmable HSDS,

AC-LVPECL, LVDS and HSCL formats

– Up to 16 total frequency outputs when

configured with 6 LVCMOS frequency outputs

on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2

and 10 differential outputs on OUT2_P/N to

OUT11_P/N

– 1Hz (1PPS) to 1250MHz output frequency with

programmable swing and common mode

– PCIe Gen 1 to 6 compliant

• I2C or 3-wire/4-wire SPI

2 Applications

• 4G and 5G Wireless Networks

– Active Antenna System (AAS), mMIMO

– Macro Remote Radio Unit (RRU)

– CPRI/eCPRI Baseband, Centralized,

Distributed Units (BBU, CU, DU)

– Small cell base station

• SyncE (G.8262), SONET/SDH (Stratum 3/3E,

G.813, GR-1244, GR-253), IEEE-1588 PTP

secondary clock

• Jitter cleaning, wander attenuation, and reference

clock generation for 112G/224G PAM4 SerDes

• Optical Transport Networks (OTN G.709)

• Broadband fixed line access

• Industrial

– Test and measurement

3 Description

The LMK5C22212A is a high-performance network

synchronizer and jitter cleaner designed to meet the

stringent requirements of wireless communications

and infrastructure applications.

The network synchronizer integrates 2 DPLLs to

provide hitless switching and jitter attenuation with

programmable loop bandwidth and no external loop

filters, maximizing flexibility and ease of use. Each

DPLL phase locks a paired APLL to a reference input.

APLL1 features ultra high performance PLL with TI's

proprietary Bulk Acoustic Wave (BAW) technology

(known as the BAW APLL) and can generate output

clocks with 40fs typical / 60fs maximum 12kHz to

20MHz RMS jitter at 491.52MHz, independent of the

jitter and frequency of the XO and DPLL reference

inputs. APLL2/DPLL2 provides an option for a second

frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL

reference clocks and performs a hitless switch

between inputs upon detecting a switchover event.

Zero-Delay Mode (ZDM) and phase cancellation can

be enabled to control the phase relationship from

input to outputs.

The device is fully programmable through I2C or SPI.

The integrated EEPROM can be used to customize

system start-up clocks. The device also features

factory default ROM profiles as fallback options.