256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM

DESCRIPTION The 8 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 wor

文件：157 Kbytes 页数：20 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体

256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabric

文件：261.57 Kbytes 页数：37 Pages

ISSI

矽成半导体