SDR SDRAM

·Synchronous, with 3.3V power supply\n·LVTTL interface\n·Programmable burst length (1, 2, 4, 8, full page)\n·Programmable burst sequence: Sequential/Interleave\n·Self refresh and Auto Refresh modes\n·Random column address every clock cycle\n·Programmable CAS latency (2, 3 clocks)\n·Burst read/write

ISSI

矽成半导体

8K refresh cycles every 64 ms

文件：1.71168 Mbytes 页数：68 Pages

ISSI

矽成半导体

16M x 32 512Mb SYNCHRONOUS DRAM

文件：885.4 Kbytes 页数：60 Pages

ISSI

矽成半导体

Internal bank for hiding row access/precharge

文件：1.57364 Mbytes 页数：66 Pages

ISSI

矽成半导体