GENERAL DESCRIPTIONThe DS21354/DS213554 single-chip transceivers(SCTs) contain all the necessary functions to connect toE1 lines. The devices are upward-compatible versionsof the DS2153 and DS2154 SCTs. The on-boardclock/data recovery circuitry coverts the AMI/HDB3 E1waveforms to an NRZ serial stream. Both devicesautomatically adjust to E1 22AWG (0.6mm) twistedpaircables from 0 to over 2km in length. They cangenerate the necessary G.703 waveshapes for both 75coax and 120 twisted cables. The on-board jitterattenuator (selectable to either 32 bits or 128 bits) canbe placed in either the transmit or receive data paths.The framer locates the frame and multiframeboundaries and monitors the data stream for alarms. It isalso used for extracting and inserting signaling data, Si,and Sa-bit information. The on-board HDLC controllercan be used for Sa-bit links or DS0s. The devicescontain a set of internal registers that the user canaccess to control the operation of the units. Quickaccess through the parallel control port allows a singlecontroller to handle many E1 lines. The devices fullymeet all the latest E1 specifications, including ITU-TG.703, G.704, G.706, G.823, G.732, and I.431, ETS300 011, 300 233, and 300 166, as well as CTR12 andCTR4.
FEATURESComplete E1 (CEPT) PCM-30/ISDN-PRITransceiver FunctionalityOn-Board Long- and Short-Haul Line Interfacefor Clock/Data Recovery and Waveshaping32-Bit or 128-Bit Crystal-Less Jitter AttenuatorFrames to FAS, CAS, CCS, and CRC4 FormatsIntegral HDLC Controller with 64-Byte BuffersConfigurable for Sa Bits, DS0, or Sub-DS0OperationDual Two-Frame Elastic Store Slip Buffers thatcan Connect to Asynchronous Backplanes up to8.192MHzInterleaving PCM Bus Operation8-Bit Parallel Control Port that can be usedDirectly on Either Multiplexed orNonmultiplexed Buses (Intel or Motorola)Extracts and Inserts CAS SignalingDetects and Generates Remote and AIS AlarmsProgrammable Output Clocks for Fractional E1,H0, and H12 ApplicationsFully Independent Transmit and ReceiveFunctionalityFull Access to Si and Sa Bits Aligned withCRC-4 MultiframeFour Separate Loopback Functions for TestingFunctionsLarge Counters for Bipolar and Code Violations,CRC4 Codeword Errors, FAS Word Errors, andE BitsIEEE 1149.1 JTAG-Boundary Scan ArchitecturePin Compatible with DS2154/52/352/552 SCTs3.3V (DS21354) or 5V (DS21554) Supply; LowPowerCMOS100-pin LQFP package (14mm x 14mm)
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