(1) The minimum VID value is applicable over the entire common mode range, VCM. (2) RL range: 90 ??RL ? 110 ?. (3) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use VCC_CLKIN that must be powered by 2.5 V. Differential clock inputs in row I/O banks are powered by VCCPD. (4) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 0.85 V ??VIN ??1.75 V. The receiver voltage input range for the data rate when Dmax ??700 Mbps is 0.45 V ??VIN ??1.95 V. (5) Power supply for the column I/O LVPECL differential clock input buffer is VCC_CLKIN. (6) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 1.0 V ??VIN ??1.6 V. The receiver voltage input range for the data rate when Dmax ??700 Mbps is zero V ??VIN ??1.85 V.
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