The Stratix? II GX family of devices is Altera’s third generation of FPGAs to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix II GX devices include 4 to 20 high-speed transceiver channels, each incorporating clock and data recovery unit (CRU) technology and embedded SERDES capability at data rates of up to 6.375 gigabits per second (Gbps). The transceivers are grouped into four-channel transceiver blocks and are designed for low power consumption and small die size. The Stratix II GX FPGA technology is built upon the Stratix II architecture and offers a 1.2-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix II GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications. Features This section lists the Stratix II GX device features. ■ Main device features: ● TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 550 MHz ● Up to 16 global clock networks with up to 32 regional clock networks per device region ● High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters ● Up to four enhanced PLLs per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting ● Support for numerous single-ended and differential I/O standards ● High-speed source-synchronous differential I/O support on up to 71 channels ● Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1 ● Support for high-speed external memory, including quad data rate (QDR and QDRII) SRAM, double data rate (DDR and DDR2) SDRAM, and single data rate (SDR) SDRAM
● Support for multiple intellectual property megafunctions from Altera? MegaCore? functions and Altera Megafunction Partners Program (AMPPSM) megafunctions ● Support for design security using configuration bitstream encryption ● Support for remote configuration updates ■ Transceiver block features: ● High-speed serial transceiver channels with clock data recovery (CDR) provide 600-megabits per second (Mbps) to 6.375-Gbps full-duplex transceiver operation per channel ● Devices available with 4, 8, 12, 16, or 20 high-speed serial transceiver channels providing up to 255 Gbps of serial bandwidth (full duplex) ● Dynamically programmable voltage output differential (VOD) and pre-emphasis settings for improved signal integrity ● Support for CDR-based serial protocols, including PCI Express, Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G, CPRI, Serial RapidIO, SONET/SDH ● Dynamic reconfiguration of transceiver channels to switch between multiple protocols and data rates ● Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation ● Adaptive equalization (AEQ) capability at the receiver to compensate for changing link characteristics ● Selectable on-chip termination resistors (100, 120, or 150 Ω) for improved signal integrity on a variety of transmission media ● Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer ● 1.2- and 1.5-V pseudo current mode logic (PCML) for 600 Mbps to 6.375 Gbps (AC coupling) ● Receiver indicator for loss of signal (available only in PIPE mode) ● Built-in self test (BIST) ● Hot socketing for hot plug-in or hot swap and power sequencing support without the use of external devices ● Rate matcher, byte-reordering, bit-reordering, pattern detector, and word aligner support programmable patterns ● Dedicated circuitry that is compliant with PIPE, XAUI, and GIGE ● Built-in byte ordering so that a frame or packet always starts in a known byte lane ● Transmitters with two PLL inputs for each transceiver block with independent clock dividers to provide varying clock rates on each of its transmitters
● 8B/10B encoder and decoder perform 8-bit to 10-bit encoding and 10-bit to 8-bit decoding ● Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array ● Receiver FIFO resynchronizes the received data with the local reference clock ● Channel aligner compliant with XAUI
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