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TMS320DM368ZCE斯普仑原装现货销售

2023-2-27 10:31:00
  • 1 TMS320DM368 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 ? Highlights ? ARM926EJ-S? Core – High-Performance Digital Media – Support for

1 TMS320DM368 Digital Media System-on-Chip (DMSoC)

1.1 Features

12

? Highlights ? ARM926EJ-S? Core

– High-Performance Digital Media – Support for 32-Bit and 16-Bit

System-on-Chip (DMSoC) (Thumb? Mode) Instruction Sets

– 432-MHz ARM926EJ-S Clock Rate – DSP Instruction Extensions and Single Cycle

– Two Video Image Co-processors MAC

(HDVICP, MJCP) Engines – ARM? Javelle? Technology

– Supports a Range of Encode, Decode, and – Embedded ICE-RT Logic for Real-Time

Video Quality Operations Debug

– Video Processing Subsystem ? ARM9 Memory Architecture

? HW Face Detect Engine – 16K-Byte Instruction Cache

? Resize Engine from 1/16x to 8x – 8K-Byte Data Cache

? 16-Bit Parallel AFE (Analog Front-End) – 32K-Byte RAM

Interface Up to 120 MHz – 16K-Byte ROM

? 4:2:2 (8-/16-bit) Interface – Little Endian

? 3 DACs for HD Analog Video Output

? Two Video Image Co-processors

? Hardware On-Screen Display (OSD) (HDVICP, MJCP) Engines

– Capable of 1080p 30fps H.264 video – Support a Range of Encode and Decode

processing Operations

– Peripherals include EMAC, USB 2.0 OTG, – H.264, MPEG4, MPEG2, MJPEG, JPEG,

DDR2/NAND, 5 SPIs, 2 UARTs, 2 WMV9/VC1

MMC/SD/SDIO, Key Scan ? Video Processing Subsystem

– 8 Different Boot Modes and Configurable – Front End Provides:

Power-Saving Modes

? HW Face Detect Engine

– Pin-to-pin and software compatible with

? Hardware IPIPE for Real-Time Image

DM365

Processing

– Extended temperature (-40oC – 85oC)

– Resize Engine

available

– Resize Images From 1/16x to 8x

– 3.3-V and 1.8-V I/O, 1.35-V Core

– Separate Horizontal/Vertical

– Debug Interface Support Control

– 338-Pin Ball Grid Array at 65nm Process

– Two Simultaneous Output Paths

Technology

? IPIPE Interface (IPIPEIF)

? High-Performance Digital Media

? Image Sensor Interface (ISIF) and CMOS

System-on-Chip (DMSoC)

Imager Interface

– 432-MHz ARM926EJ-S Clock Rate

? 16-Bit Parallel AFE (Analog Front End)

– 4:2:2 (8-/16-Bit) Interface

Interface Up to 120 MHz

– Capable of 1080p 30fps H.264 video

? Glueless Interface to Common Video

processing Decoders

– Pin compatible with DM365 processors

? BT.601/BT.656/BT.1120 Digital YCbCr

– Fully Software-Compatible With ARM9? 4:2:2 (8-/16-Bit) Interface

– Extended temperature available for 432-Mhz ? Histogram Module

device

? Lens distortion correction module (LDC) configurable as two 32-bit timers)

– Back End Provides: ? One 64-Bit Watch Dog Timer

? Hardware On-Screen Display (OSD) ? Two UARTs (One fast UART with RTS and CTS

Flow Control)

? Composite NTSC/PAL video encoder

output ? Five Serial Port Interfaces (SPI) each with two

? 8-/16-bit YCC and Up to 24-Bit RGB888 Chip-Selects

Digital Output ? One Master/Slave Inter-Integrated Circuit

(I

2

? 3 DACs for HD Analog Video Output C) Bus?

? One Multi-Channel Buffered Serial Port

? LCD Controller

(McBSP)

? BT.601/BT.656 Digital YCbCr 4:2:2

(8-/16-Bit) Interface – I2S

? Analog-to-Digital Convertor (ADC) – AC97 Audio Codec Interface

? Power Management and Real Time Clock – S/PDIF via Software

Subsystem (PRTCSS) – Standard Voice Codec Interface (AIC12)

– Real Time Clock – SPI Protocol (Master Mode Only)

? 16-Bit Host-Port Interface (HPI) – Direct Interface to T1/E1 Framers

? 10/100 Mb/s Ethernet Media Access Controller – Time Division Multiplexed Mode (TDM)

(EMAC) - Digital Media – 128 Channel Mode

– IEEE 802.3 Compliant

? Four Pulse Width Modulator (PWM) Outputs

– Supports Media Independent Interface (MII)

? Four RTO (Real Time Out) Outputs

– Management Data I/O (MDIO) Module ? Up to 104 General-Purpose I/O (GPIO) Pins

? Key Scan (Multiplexed with Other Device Functions)

? Voice Codec ? Boot Modes

? External Memory Interfaces (EMIFs) – On-Chip ARM ROM Bootloader (RBL) to Boot

– DDR2 and mDDR SDRAM 16-bit wide EMIF From NAND Flash, MMC/SD, UART, USB,

With 256 MByte Address Space SPI, EMAC, or HPI

(1.8-V I/O)

– Asynchronous16-/8-bit Wide EMIF – AEMIF (NOR and OneNAND)

(AEMIF)

? Flash Memory Interfaces ? Configurable Power-Saving Modes

– NAND (8-/16-bit Wide Data)

? Crystal or External Clock Input (typically

19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)

– 16 MB NOR Flash, SRAM

? Flexible PLL Clock Generators

– OneNAND(16-bit Wide Data)

? Debug Interface Support

? Flash Card Interfaces

– IEEE-1149.1 (JTAG?)

– Two Multimedia Card (MMC) / Secure Digital

Boundary-Scan-Compatible

(SD/SDIO)

– ETB (Embedded Trace Buffer) with 4K-Bytes

– SmartMedia/xD

Trace Buffer memory

? Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

– Device Revision ID Readable by ARM

? 338-Pin Ball Grid Array (BGA) Package

? USB Port with Integrated 2.0 High-Speed PHY

(ZCE Suffix), 0.65-mm Ball Pitch

that Supports

? 65nm Process Technology

– USB 2.0 High-Speed Device

? 3.3-V and 1.8-V I/O, 1.35-V Internal

– USB 2.0 High-Speed Host (mini-host,

supporting one external device)

? Community Resources

– USB On The Go (HS-USB OTG) – TI E2E Community

– TI Embedded Processors Wiki

? Four 64-Bit General-Purpose Timers (each

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