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RTD1186DD-GR
RTD1186DA-GR
RTD1186MD-GR
RTD1186MA-GR
RTD1186PA-GR
FULL HD MULTI-FORMAT MULTIMEDIA
DECODER WITH HIGH-SPEED INTERFACES,
10/100/1000M ETHERNET, HDMI, AND DTV
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
05 August 2011
Track ID: CONF-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTD1186 controller ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0 2011/06/30 First release.
1.1 2011/07/21 Revised section 26 Mechanical Dimensions, page 60.
1.2 2011/08/05 Added RTD1186PA-GR model number.
Revised Table 1 Pin Descriptions, page 8.
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1. General Description
The RTD1186DD-GR/RTD1186DA-GR/RTD1186MD-GR/RTD1186MA-GR/RTD1186PA-GR is a
highly integrated SoC for Consumer Electronic products requiring High Definition Media Playback,
Wireless/Wired Networking, Mass Storage, and DTV capabilities.
Main features of the RTD1186 include HD MPEG1/2/4/H.264/H.264 MVC & HD JPEG Decoder, HD
AVC/VC-1 Decoder, HD RM/RMVB Decoder, HD AVS Decoder, DTV Recording & Timeshifting, AV
Streaming/Transmission via Ethernet & WiFi, TV Encoder with CVBS/YPbPr/SCART out, I
2
S in/out,
SPDIF out, HDMI Transmitter and PHY, OTP (One-Time Programmable ROM), dual USB 2.0 Host or
one USB 2.0 Host/Device with dual port integrated PHY, USB 3.0 Host/Device, NAND/NOR flash
controller, SATA, PCI Express, Card reader supporting SD/MMC/MS Pro, high-speed UART for
Bluetooth, 10/100M Ethernet MAC and PHY, and Gigabit Ethernet MAC.
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2. Features
„ System and Peripherals
‹ Operating System: Linux
‹ 1200 DMIPS MIPS processor with FPU
‹ OpenGL ES2.0-compliant POWERVR
SGX 3D GPU from Imagination
Technology
‹ MIPS 4Kec secure processor
‹ Video DSP with HW acceleration
‹ Audio DSP with HW acceleration
‹ Supports up to 2GB DDR3 SDRAM
with 32-bit data interface
‹ Supports Serial NOR Flash with dual I/O
data interface
‹ Supports NAND Flash
‹ Boot-ROM and OTP (One-Time
Programmable) ROM for Secure-Boot
and Key storage
‹ Integrated SATA 2.0 MAC and PHY
‹ Integrated Fast Ethernet MAC and PHY
‹ Integrated Gigabit Ethernet MAC
‹ Integrated USB 3.0 Super-Speed
Host/Device controller and PHY
‹ Integrated dual USB 2.0 High-Speed
Host controller, or one Host/Device
controller, and Dual PHY
‹ Integrated PCI Express interface MAC
and PHY
‹ Supports Network applications
‹ Supports SD/MMC/MS PRO Cards
‹ Supports UART/IrDA/I
2
C/GPIO/
EJTAG/VFD/RTC
„ Audio Interface and Function
‹ Built-in Audio DAC with 24-bit
resolution
‹ One 2-CH I
2
S interface for audio output
‹ One 2-CH I
2
S interface for audio input
‹ IEC60958 (SPDIF) digital audio output
‹ 7.1 down-mix
‹ MPEG I Layer 1, 2, 3 (2-CH) and MPEG
II Layer 1, 2 (Multi-Channel)
‹ LPCM, ADPCM, FLAC, AAC, WAV,
and OGG Vorbis
‹ DTS HD Master Audio, High Resolution,
Low Bit Rate (LBR)
‹ Dolby Digital Plus, TrueHD
‹ RA1/RA-cook/RA-lossless
‹ WMA/WMA Pro, Dolby Digital AC3
and DTS® (Licensee Only)
‹ LPCM/ADPCM/MPEG/AAC audio
recording
„ Video Interface
‹ Dual Serial TS inputs for Digital TV
systems
‹ TV encoder with four 12-bit video D/A
converters
‹ NTSC and PAL TV systems
‹ Composite analog video outputs
‹ Component (YPbPr or RGB) analog
video output
‹ Simultaneous Composite and YPbPr
output
‹ Simultaneous SD/HD output
‹ HDMI version 1.4 transmitter with CEC
and support for 3D over HDMI
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‹ Supports SCART output
‹ 3D De-interlacer
‹ Bitmap OSD
„ Video and Picture Function
‹ Media Browser and Player
‹ Supports Subtitles
‹ Photo slideshow with transition effects
‹ DTV function
‹ Photo slideshow with transition effects
‹ Supports simultaneous dual HD decode
‹ MPEG1, VCD 1.0/2.0, SVCD
‹ Supports HD MPEG2 (up to MP@HL
1080p), ISO/IFO/VOB/TS
‹ Supports HD MPEG4 SP/ASP
(720p/1080i/1080p), Xvid
‹ H.264 BP@L4.1, HP@L4.1
‹ WMV7, 8, 9/VC-1 AP@L3
‹ RealVideo 8/9/10, up to 1080@30P
‹ DivX3/4/5/6 (Licensee Only)
‹ AVS HD 1920x1080
‹ HW VP6 Decoder
‹ H.264 MVC HP@L4.1
‹ Stereoscopic 1920x1080@30P
‹ HD JPEG with unlimited resolution
(40M-pixel tested)
‹ Full-pixel JPEG decode with high
resolution zoom-in
‹ De-blocking/De-ringing Filter
‹ Video upscaling from SD to HD
(720p/1080i/1080p)
‹ Supports 24/30/36-bit deep color
„ Copy Protection
‹ CGMS-A
‹ HDCP
‹ Microsoft DRM
‹ Secure Boot with OTP and embedded
boot-ROM
‹ Rovi (formerly Macrovision)
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3. System Applications
„ HD Media Player
„ Digital Media Adaptor/Server
„ STB with PVR (Personal Video Recorder)
„ Networked Media Module for Embedded CE devices
3.1. Application Diagram
Figure 1. Application Diagram
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4. Block Diagram
Peripheral
GPIO
UART
IR
I
2
C VFD Ctrl.
Timer Ctrl. USB2/3
Host &
Device
Gb
ETN
Mac
Flash
Ctrl.
DDR3
Ctrl.
HDMI
TV
Encoder
SPDIF Output I
2
S I/O
10/100
ETN
MAC &
PHY
OTP
ROM
RTC
PLL
PCI-E
SATA
Card
Reader
TS I/O
Audio
Engine
Video
Engine
1200 DMIPS
MIPS processor
MIPS 4Kec
SGX 3D GPU
Figure 2. Block Diagram
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5. Pin Assignments
5.1. Package Identification
XX in the model number indicates DD, DA, MD, MA, or PA model. Green package is indicated by the
‘G’ in GXXXX (Figure 3)
A B C D E F G H J K L M N P R T U V W Y
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 3. Package Identification
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5.2. Pin Assignments (Bottom View)
Figure 4. Pin Assignments (Bottom View)
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6. Pin Descriptions
DI: Digital Input AI: Analog Input
DO: Digital Output AO: Analog Output
DB: Digital Bi-directional AB: Analog Bi-directional
GND: Ground PWR: Power Supply
Table 1. Pin Descriptions
Pin No. Pin Name I/O Description
VFD_CLK DO VFD Controller Clock A1
IGPIO4 DB Isolation General Purpose IO 4
A2 UART0_TX DO UART 0 Transmit Data Output
SPI_SI/SIO0 DB Serial Flash Data Input
GPIO0 DB General Purpose IO 0
A3
UR2_CTS# DI UART 2 Clear to Send Input for Bluetooth
A4 REXT PWR External Reference Resistor
A5 VDAC_D AO Composite
A6 AO_L AO Audio DAC Output Left Channel
A7 VRP PWR Positive Reference Voltage for Audio DAC
A8 NC - Not Connected
A9 HDMI_D2N AO HDMI Output Data Pair 2-
A10 HDMI_D1N AO HDMI Output Data Pair 1-
A11 HDMI_D0N AO HDMI Output Data Pair 0-
A12 HDMI_CKN AO HDMI Output Clock Pair-
RXCTL DI Transmit Control Signal from PHY to MAC A13
GPIO87 DB General Purpose IO 87
RXD2 DI RGMII Receive Data A14
GPIO66 DB General Purpose IO 66
TXC DO RGMII Transmit Clock A15
GPIO113 DB General Purpose IO 113
TXD3 DO RGMII Transmit Data A16
GPIO114 DB General Purpose IO 114
GPHY_CLK25 DO RTD1186 Output to External Giga PHY 25MHz Clock Input A17
GPIO88 DB General Purpose IO 88
A18 ETN_RXIP AI Ethernet 10/100Mbps Receive Input Pair+
A19 ETN_TXOP AO Ethernet 10/100Mbps Transmit Output Pair+
TP2_SYNC DI Primary Transport Stream Input SYNC
AO_MCLK DO Main Clock Output to DAC
A20
GPIO54 DB General Purpose IO 54
VFD_CS# DO VFD Controller Chip Select B1
IGPIO3 DB Isolation General Purpose IO 3
B2 UART0_RX DI UART 0 Receive Data Input
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Pin No. Pin Name I/O Description
SPI_SCK DO Serial Flash Clock
GPIO1 DB General Purpose IO 1
B3
UR2_TX DO UART 2 Transmit Data Output for Bluetooth
B4 VDAC_B AO Component Analog Video Blue or Pb
B5 VDAC_A AO Component Analog Video Green or Luminance
B6 AO_R AO Audio DAC Output Right Channel
B7 VREF PWR Common Mode Reference Voltage for Audio DAC
B8 NC - Not Connected
B9 HDMI_D2P AO HDMI Output Data Pair 2+
B10 HDMI_D1P AO HDMI Output Data Pair 1+
B11 HDMI_D0P AO HDMI Output Data Pair 0+
B12 HDMI_CKP AO HDMI Output Clock Pair+
RXD0 DI RGMII Receive Data B13
GPIO70 DB General Purpose IO 70
RXD3 DI RGMII Receive Data B14
GPIO65 DB General Purpose IO 65
TXD0 DO RGMII Transmit Data B15
GPIO117 DB General Purpose IO 117
TXCTL DO Transmit Control Signal from MAC to PHY B16
GPIO118 DB General Purpose IO 118
B17 ETN_RXIN AI Ethernet 10/100Mbps Receive Input Pair-
B18 ETN_TXON AO Ethernet 10/100Mbps Transmit Output Pair-
TP2_VALID DI Primary Transport Stream Input Data Valid
AO_BCLK DO I
2
S Bit Clock Output to DAC
B19
GPIO55 DB General Purpose IO 55
TP2_CLK DI Primary Transport Stream Input Clock
AO_LRCK DO I
2
S Word Select Clock Output to DAC
B20
GPIO53 DB General Purpose IO 53
ETN_ACT DO RX/TX LED for ETN C1
IGPIO9 DB Isolation General Purpose IO 9
VFD_D DB VFD Controller Data Input/Output C2
IGPIO5 DB Isolation General Purpose IO 5
SPI_CE# DO Serial Flash Chip Enable
GPIO2 DB General Purpose IO 2
C3
UR2_RX DI UART2 Receive Data Input for Bluetooth
C4 VDAC_C AO Component Analog Video Red or Pr
C5 VDAC_GND GND Video DAC Ground
C6 ADAC_GND GND Audio DAC Ground
C7 ADAC_3.3V PWR Audio DAC Power 3.3V
C8 1.0V PWR Power 1.0V
C9 HDMI_HPD DI HDMI Hot Plug Detect
C10 HDMI_GND GND HDMI Ground
C11 HDMI_CEC AB HDMI Consumer Electronics Control
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Pin No. Pin Name I/O Description
I2C0_SDA DB I
2
C 0 Serial Data C12
GPIO62 DB General Purpose IO 62
RXD1 DI RGMII Receive Data C13
GPIO67 DB General Purpose IO 67
RXC DI RGMII Receive Clock C14
GPIO9 DB General Purpose IO 9
TXD1 DO RGMII Transmit Data C15
GPIO116 DB General Purpose IO 116
MDC DO Management Data Clock C16
GPIO86 DB General Purpose IO 86
C17 ETN_GND GND Ethernet Ground
I2C1_SCL DB I
2
C Serial Clock C18
GPIO63 DB General Purpose IO 63
TP2_DATA DI Primary Transport Stream Input Data
AO_SD0 DO I
2
S Serial Data Output for Downmixing Channels
C19
GPIO56 DB General Purpose IO 56
TP3_SYNC DI Secondary Transport Stream Input SYNC
AI_SD0 DI I
2
S Serial Data Input for Audio L/R Input
PWM1 DO PWM1 Output
C20
GPIO5 DB General Purpose IO 5
ETN_LINK DO Link LED for ETN D1
IGPIO8 DB Isolation General Purpose IO 8
D2 IGPIO0 DB Power Control in Standby Mode: Isolation General Purpose IO 0
SPI_SO/SIO1 DB Serial Flash Data Output
GPIO3 DB General Purpose IO 3
D3
UR2_RTS# DO UART2 Request to Send Output for Bluetooth
D4 VDAC_GND GND Video DAC Ground
D5 VDAC_3.3V PWR Video DAC Power 3.3V
D6 VDAC_3.3V PWR Video DAC Power 3.3V
D7 3.3V PWR Power 3.3V
D8 HDMI_1.0V PWR HDMI Reference Pin
D9 HDMI_3.3V PWR HDMI Power 3.3V
D10 HDMI_GND GND HDMI Ground
D11 HDMI_GND GND HDMI Ground
I2C0_SCL DB I
2
C 0 Serial Clock D12
GPIO61 DB General Purpose IO 61
SPDIF_OUT DO IEC60958 (SPDIF) Output D13
GPIO7 DB General Purpose IO 7
D14 GND GND Digital Ground
TXD2 DO RGMII Transmit Data D15
GPIO115 DB General Purpose IO 115
MDIO DB Management Data Input/Output D16
GPIO8 DB General Purpose IO 8
D17 ETN_3.3V PWR Ethernet Power 3.3V
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Pin No. Pin Name I/O Description
I2C1_SDA DB I
2
C Serial Data D18
GPIO64 DB General Purpose IO 64
TP3_VALID DI Secondary Transport Stream Input Data Valid
AI_LRCK DO I
2
S Word Select Clock Output to ADC
PWM0 DO PWM0 Output
D19
GPIO4 DB General Purpose IO 4
TP3_CLK DI Secondary Transport Stream Input Clock
AI_MCLK DO Main Clock Output to ADC as Master mode
D20
GPIO57 DB General Purpose IO 57
IR_IN DI Infrared Input from IR Receiver E1
IGPIO6 DB Isolation General Purpose IO 6
E2 RESET# DI Chip Reset
E3 ISO_1.0V PWR Isolation Block Power 1.0V
E4 ISO_1.0V PWR Isolation Block Power 1.0V
E17 ETN_1.0V PWR Ethernet Power 1.0V
E18 GND GND Digital Ground
TP3_DATA DI Secondary Transport Stream Input Data
AI_BCLK DO I
2
S Bit Clock Output to ADC
E19
GPIO58 DB General Purpose IO 58
TP5_CLK DO Transport Stream Output Clock
GSPI_SCK DO Serial Interface Clock
E20
GPIO121 DB General Purpose IO 121
F1 RTC_XO AO 32.768kHz Crystal Oscillator Output
F2 RTC_XI AI 32.768kHz Crystal Oscillator Input
F3 RTC_3.3V PWR RTC Power 3.3V
F4 PLL_1.0V PWR PLL Power 1.0V
F17 GPIO60 DB General Purpose IO 60
F18 GPIO122 DB General Purpose IO 122
TP5_VALID DI Transport Stream Output Data Valid
GSPI_CE# DO Serial Interface Chip Select Output
F19
GPIO120 DB General Purpose IO 120
TP5_DATA DO Transport Stream Output Data
GSPI_SI/SIO0 DB
Serial Data Input (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O read mode)
F20
GPIO10 DB General Purpose IO 10
G1 XTLO AO 27MHz Crystal Oscillator Output
G2 XTLI AI 27MHz Crystal Oscillator Input
G3 PLL_GND GND PLL Ground
G4 PLL_3.3V PWR PLL Power 3.3V
G17 N_FLASH DI NAND Flash Selection
G18 TESTMODE DI Select Test Mode
USB2_Flag3# DI In Host Mode: USB2 Port3 Over-Current Detect G19
USB2_VBUS DI In Device Mode: USB2 Port3 VBUS-In Detect
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Pin No. Pin Name I/O Description
TP5_SYNC DO Transport Stream Output SYNC
GSPI_SO/SIO1 DB
Serial Data Output (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O Read Mode)
G20
GPIO11 DB General Purpose IO 11
USB2_Flag2# DI USB2 Port2 Over-Current Detect H1
IGPIO1 DB Isolation General Purpose IO 1
USB3_Flag1# DI In Host Mode: USB3 Over-Current Detect
USB3_VBUS DI In Device Mode: USB3 VBUS-In Detect
H2
IGPIO2 DB Isolation General Purpose IO 2
H3 USB3_TX_1.0V PWR USB3 TX Power 1.0V
H4 USB3_3.3V PWR USB3 Power 3.3V
H8 3.3V PWR Digital I/O Power 3.3V
H9 3.3V PWR Digital I/O Power 3.3V
H10 GND GND Digital Ground
H11 GND GND Digital Ground
H12 GND GND Digital Ground
H13 GND GND Digital Ground
H17 DDRPLL_1.0V PWR DDR3 PLL Power 1.0V
H18 DDRPLL_GND PWR DDR3 PLL Ground
H19 1.5V PWR DDR3 Power
H20 GND GND Digital Ground
J1 USB3_TXN AO Port1 USB3 TX- Signal
J2 USB3_TXP AO Port1 USB3 TX+ Signal
J3 USB3_TX_GND GND USB3 TX Ground
J4 USB3_RX_1.0V PWR USB3 RX Power 1.0V
J8 3.3V PWR Digital I/O Power 3.3V
J9 GND GND Digital Ground
J10 GND GND Digital Ground
J11 GND GND Digital Ground
J12 GND GND Digital Ground
J13 GND GND Digital Ground
J17 DDR3_DQ26 DB DDR3 Data Bit 26
J18 DDR3_DQ24 DB DDR3 Data Bit 24
J19 DDR3_DQ23 DB DDR3 Data Bit 23
J20 DDR3_DQ21 DB DDR3 Data Bit 21
K1 USB3_RXN AI Port 1 USB3 RX- Signal
K2 USB3_RXP AI Port 1 USB3 RX+ Signal
K3 USB3_RX_GND GND USB3 RX Ground
K4 USB2_GND GND USB2 Ground
K8 1.0V PWR Core Power 1.0V
K9 1.0V PWR Core Power 1.0V
K10 1.0V PWR Core Power 1.0V
K11 1.0V PWR Core Power 1.0V
K12 1.0V PWR Core Power 1.0V
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Pin No. Pin Name I/O Description
K13 1.0V PWR Core Power 1.0V
K17 DDR3_DQ28 DB DDR3 Data Bit 28
K18 DDR3_DQ30 DB DDR3 Data Bit 30
K19 DDR3_DQ17 DB DDR3 Data Bit 17
K20 DDR3_DQ19 DB DDR3 Data Bit 19
L1 USB2_DM1 AB Port 1 USB2 D- Signal
L2 USB2_DP1 AB Port 1 USB2 D+ Signal
L3 USB2_GND GND USB2 Ground
L4 USB2_GND GND USB2 Ground
L8 1.0V PWR Core Power 1.0V
L9 1.0V PWR Core Power 1.0V
L10 1.0V PWR Core Power 1.0V
L11 1.0V PWR Core Power 1.0V
L12 1.0V PWR Core Power 1.0V
L13 1.0V PWR Core Power 1.0V
L17 DDR3_UUDQS DB DDR3 DQ[31:24] Data Strobe
L18 DDR3_UUDQS# DB DDR3 DQ[31:24] Data Strobe
L19 GND GND Digital Ground
L20 DDR3_ULDM DO DDR3 DQ[23:16] Data Mask
M1 USB2_DM2 AB Port 2 USB2 D- Signal
M2 USB2_DP2 AB Port 2 USB2 D+ Signal
M3 USB2_GND GND USB2 Ground
M4 USB2_3.3V PWR USB2 Power 3.3V
M8 GND GND Digital Ground
M9 GND GND Digital Ground
M10 GND GND Digital Ground
M11 GND GND Digital Ground
M12 1.5V PWR DDR3 Power
M13 1.5V PWR DDR3 Power
M17 DDR3_UUDM DO DDR3 DQ[31:24] Data Mask
M18 1.5V PWR DDR3 Power
M19 DDR3_ULDQS DB DDR3 DQ[23:16] Data Strobe
M20 DDR3_ULDQS# DB DDR3 DQ[23:16] Data Strobe
N1 USB2_DM3 AB Port 3 USB2 D- Signal
N2 USB2_DP3 AB Port 3 USB2 D+ Signal
N3 USB2_GND GND USB2 Ground
N4 USB2_3.3V PWR USB2 Power 3.3V
N8 GND GND Digital Ground
N9 GND GND Digital Ground
N10 GND GND Digital Ground
N11 GND GND Digital Ground
N12 1.5V PWR DDR3 Power
N13 1.5V PWR DDR3 Power
N17 DDR3_DQ29 DB DDR3 Data Bit 29
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Pin No. Pin Name I/O Description
N18 DDR3_DQ31 DB DDR3 Data Bit 31
N19 DDR3_DQ18 DB DDR3 Data Bit 18
N20 DDR3_DQ16 DB DDR3 Data Bit 16
P1 SATA_HSIP AI SATA RX Channel Positive Input
P2 SATA_HSIN AI SATA RX Channel Negative Input
P3 USB2_GND GND USB2 Ground
P4 USB2_1.0V PWR USB2 Power 1.0V
P17 DDR3_DQ27 DB DDR3 Data Bit 27
P18 DDR3_DQ25 DB DDR3 Data Bit 25
P19 DDR3_DQ20 DB DDR3 Data Bit 20
P20 DDR3_DQ22 DB DDR3 Data Bit 22
R1 SATA_HSON AO SATA TX Channel Negative Output
R2 SATA_HSOP AO SATA TX Channel Positive Output
R3 SATA_GND GND SATA Ground
R4 SATA_1.0V PWR SATA Power 1.0V
R17 DVRI PWR DDR3 Reference Voltage Input
R18 DDR3_A5 DO DDR3 Address Bit 5
R19 DDR3_A7 DO DDR3 Address Bit 7
R20 DDR3_A5-1 DO DDR3 Address Bit 5 for 2nd DDR3 Chip
T1 PCIE_RXP AI PCI Express RX+
T2 PCIE_RXN AI PCI Express RX-
T3 PCIE_1.0V PWR PCI Express Power 1.0V
T4 PCIE_3.3V PWR PCI Express Power 3.3V
T17 DZQ PWR DDR3 ZQ Calibration
T18 DDR3_RESET# DO DDR3 Reset
T19 DDR3_A13 DO DDR3 Address Bit 13
T20 DDR3_A9 DO DDR3 Address Bit 9
U1 PCIE_CLKP AO PCI Express Clock+
U2 PCIE_CLKN AO PCI Express Clock-
U3 PCIE_GND GND PCI Express Ground
U4 GND GND Digital Ground
SD_CD# DI SD/MMC Card Detect
MS_CLK DO MS/MS Pro Card Clock Output
U5
GPIO12 DB General Purpose IO 12
U6 GPIO31 DB General Purpose IO 31
U7 GND GND Digital Ground
U8 DDR3_DQ9 DB DDR3 Data Bit 9
U9 DDR3_DQ15 DB DDR3 Data Bit 15
U10 DDR3_LUDM DO DDR3 DQ[15:8] Data Mask
U11 DDR3_LUDQS# DB DDR3 DQ[15:8] Data Strobe
U12 DDR3_DQ14 DB DDR3 Data Bit 14
U13 DDR3_DQ8 DB DDR3 Data Bit 8
U14 1.5V PWR DDR3 Power
U15 DDR3_CAS# DO DDR3 Column Address Select Output
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Pin No. Pin Name I/O Description
U16 DDR3_WE# DO DDR3 Write Enable Output
U17 1.5V PWR DDR3 Power
U18 GND GND Digital Ground
U19 DDR3_A3 DO DDR3 Address Bit 3
U20 DDR3_A2 DO DDR3 Address Bit 2
V1 PCIE_TXP AO PCI Express TX+
V2 PCIE_TXN AO PCI Express TX-
V3 GND GND Digital Ground
NAND_RDY DI NAND Flash Ready V4
GPIO26 DB General Purpose IO 26
NAND_CE1# DO NAND Flash Chip Enable 1
SD_WP DI SD/MMC Write Protect
MS_INS# DI MS/MS Pro Card Detect
V5
GPIO13 DB General Purpose IO 13
NAND_CE0# DO NAND Flash Chip Enable 0 V6
GPIO44 DB General Purpose IO 44
V7 GND GND Digital Ground
V8 DDR3_DQ11 DB DDR3 Data Bit 11
V9 DDR3_DQ13 DB DDR3 Data Bit 13
V10 1.5V PWR DDR3 Power
V11 DDR3_LUDQS DB DDR3 DQ[15:8] Data Strobe
V12 DDR3_DQ12 DB DDR3 Data Bit 12
V13 DDR3_DQ10 DB DDR3 Data Bit 10
V14 GND GND Digital Ground
V15 DDR3_RAS# DO DDR3 Row Address Select Output
V16 DDR3_ODT DO DDR3 On-Die-Termination
V17 DDR3_CS# DO DDR3 Chip Select Output
V18 DDR3_A15 DO DDR3 Address Bit 15
V19 DDR3_BA0 DO DDR3 Bank Address Bit 0
V20 DDR3_A0 DO DDR3 Address Bit 0
NAND_D0 DB NAND Flash Data Bit 0 W1
GPIO14 DB General Purpose IO 14
NAND_D2 DB NAND Flash Data Bit 2 W2
GPIO16 DB General Purpose IO 16
NAND_D4 DB NAND Flash Data Bit 4 (NAND/ECC Select 0) W3
GPIO18 DB General Purpose IO 18
NAND_D6 DB NAND Flash Data Bit 6 W4
GPIO20 DB General Purpose IO 20
NAND_RD# DO NAND Flash Read Enable
SD_D[0] DB SD/MMC Data 0
W5
GPIO22 DB General Purpose IO 22
SD_CMD DB SD/MMC Card Command Line
MS_D[1] DB MS/MS Pro Data 1
W6
GPIO27 DB General Purpose IO 27
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Pin No. Pin Name I/O Description
NAND_ALE DO NAND Flash Address Latch Enable
SD_D[2] DB SD/MMC Data 2
MS_D[2] DB MS/MS Pro Data 2
W7
GPIO25 DB General Purpose IO 25
W8 DDR3_DQ6 DB DDR3 Data Bit 6
W9 DDR3_DQ0 DB DDR3 Data Bit 0
W10 DDR3_LLDQS# DB DDR3 DQ[7:0] Data Strobe
W11 GND GND Digital Ground
W12 DDR3_DQ3 DB DDR3 Data Bit 3
W13 DDR3_DQ5 DB DDR3 Data Bit 5
W14 DDR3_CK# DO DDR3 Inverse Clock Output
W15 DDR3_A10 DO DDR3 Address Bit 10
W16 DDR3_A12 DO DDR3 Address Bit 12
W17 DDR3_A1 DO DDR3 Address Bit 1
W18 DDR3_A6 DO DDR3 Address Bit 6
W19 DDR3_A11 DO DDR3 Address Bit 11
W20 DDR3_BA2 DO DDR3 Bank Address Bit 2
NAND_D1 DB NAND Flash Data Bit 1 Y1
GPIO15 DB General Purpose IO 15
NAND_D3 DB NAND Flash Data Bit 3 Y2
GPIO17 DB General Purpose IO 17
NAND_D5 DB NAND Flash Data Bit 5 (NAND/ECC Select 1) Y3
GPIO19 DB General Purpose IO 19
NAND_D7 DB NAND Flash Data Bit 7
SD_D[1] DB SD/MMC Data 1
Y4
GPIO21 DB General Purpose IO 21
SD_CLK DO SD/MMC Clock Output
MS_BS DB MS/MS Pro Card Bus State Line
Y5
GPIO28 DB General Purpose IO 28
NAND_CLE DO DAND Flash Command Latch Enable
SD_D[3] DB SD/MMC Data 3
MS_D[0] DB MS/MS Pro Data 0
Y6
GPIO24 DB General Purpose IO 24
NAND_WR# DO DAND Flash Write Enable
MS_D[3] DB MS/MS Pro Data 3
Y7
GPIO23 DB General Purpose IO 23
Y8 DDR3_DQ4 DB DDR3 Data Bit 4
Y9 DDR3_DQ2 DB DDR3 Data Bit 2
Y10 DDR3_LLDQS DB DDR3 DQ[7:0] Data Strobe
Y11 DDR3_LLDM DO DDR3 DQ[7:0] Data Mask
Y12 DDR3_DQ1 DB DDR3 Data Bit 1
Y13 DDR3_DQ7 DB DDR3 Data Bit 7
Y14 DDR3_CK DO DDR3 Clock Output
Y15 DDR3_CKE DO DDR3 Clock Enable Output
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Pin No. Pin Name I/O Description
Y16 DDR3_BA1 DO DDR3 Bank Address Bit 1
Y17 DDR3_A4 DO DDR3 Address Bit 4
Y18 DDR3_A4-1 DO DDR3 Address Bit 4 for 2nd DDR3 Chip
Y19 DDR3_A8 DO DDR3 Address Bit 8
Y20 DDR3_A14 DO DDR3 Address Bit 14
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7. Licenses
Supply of this product does not convey a license under the relevant intellectual property of the companies
mentioned in this section nor imply any right to use this intellectual property in any finished end-user or
ready to use final product. An independent license for such use is required and can be obtained by
contacting the company or companies concerned.
Details of features requiring licenses are not provided in this datasheet. Features requiring licenses are:
DivX
DivX and the DivX logo are registered trademarks of DivXNet-works, Inc. in the USA and other
countries.
RM/RMVB
RM/RMVB is the intellectual property of RealNetworks. The RM/RMVB licenses allow the use of the
corresponding decoder executed in the RTD1186. For details, contact RealNetworks at: RealNetworks,
Attn: Helix Community Manager, 2601 Elliott Avenue, Seattle, WA 98121, USA.
http://www.realnetworks.com.
Dolby® Digital, Digital Plus, TrueHD, Pro Logic
® II
Dolby Digital, Digital Plus, TrueHD, and Pro Logic II are intellectual properties of Dolby Labs. The
Dolby Digital, Digital Plus, TrueHD, and Pro Logic II license allow the use of the corresponding decoder
embedded in the RTD1186.
For details, contact Dolby Labs at: Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA.
DTS®
DTS is the intellectual property of Digital Theater Systems Inc. The DTS licenses allow the use of the
corresponding decoder executed in the RTD1186. For details, contact Digital Theater Systems Inc at:
DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA. http://www.dtsonline.com.
Windows Media®
Windows Media is the intellectual property of Microsoft Corporation. The Windows Media license
allows the use of the Windows Media decoders in the RTD1186. For details, contact Microsoft at:
Microsoft Corporation, One Microsoft Way, Redmond, WA 98052-6399, USA.
http://www.microsoft.com.
Windows Media DRM
Windows Media DRM 10 for Network Devices allows the RTD1186 to play back Windows Media–based
protected content that resides on another computer on a network.
For details, contact Microsoft at: Microsoft Corporation, One Microsoft Way, Redmond, WA
98052-6399, USA. http://www.microsoft.com.
Rovi (formerly Macrovision)
Rovi (formerly Macrovision) is the intellectual property of Rovi Corporation. The Rovi license allows the
use of Rovi copy protection technology in the RTD1186. For details, contact Rovi Corporation at
http://www.rovicorp.com.
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8. System Global Resources
8.1. Power Supply
It is important to provide adequate power and ground for high-speed digital and sensitive analog design.
To achieve the best performance, the power and ground pins are separated into several groups.
Table 2. Power Supply Specification
Power Min. Typ. Max. Unit Description
1.0V 1.0 1.0 - V Power Supply of Core Digital Logic
1.0V 1.0 1.0 - V Power Supply of Analog Logic
ISO_1.0V 1.0 1.0 - V Power Supply of Isolated Block Logic
1.5V 1.5 1.5 - V Power Supply of SSTL15 I/O Pad
3.3V - 3.3 - V Power Supply of I/O Pad or HW Block
RTC_3.3V 1.0 3.3 - V Power Supply of RTC Block
DVRI - 0.75 - V I/O Reference Voltage of SSTL15 Interface
8.2. Power Management
The RTD1186 provides a Sleep Mode that shuts down all PLLs and logic to save power during idle state.
Sleep Mode is entered via a software instruction sequence, and exited by a hardware reset. External
wake-up events may be selected to automatically generate a wake-up reset.
For lower power consumption in Sleep Mode, all parts of the RTD1186 can be powered off except for the
isolation block. The wake-up function still works in this Sleep Mode.
Some RTD1186 modules could be individually powered down by gating off their clock tree. Those
modules can be powered on without resetting the whole chip.
8.3. Electrical Characteristics of LVTTL I/O Pads
Table 3. LVTTL Specification
Symbol Parameter Min. Typ. Max. Unit Condition
VIH HIGH Level Input Voltage 2.0 - - V -
VIL LOW Level Input Voltage - - 0.8 V -
VOH HIGH Level Output Voltage VCC-0.2 VCC - V -IO = 20µA
VOL LOW Level Output Voltage - - 0.4 V IO = 4.0mA
±II Input Leakage Current - 1 2 µA
VIN ≥ VIH or
VIN ≤ VIL
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8.4. Reset, Clock, and PLL
Table 4. System Global Resources External Pin Description
Pin Name IO Standard Type Description
RESET# LVTTL DI Chip Reset, Schmitt Trigger Input
XTLI Analog AI System Clock 27MHz
XTLO Analog AO System Clock 27MHz
REXT Analog PWR Bandgap Voltage of Whole Chip. Connect to GND via a 15KΩ, ±1% Resistor
The external RESET# signal is a low-active, Schmitt trigger input. To take effect, it must be held low for
at least 500ns. An external crystal (27MHz) is required for normal function, and the embedded PLL
circuit will generate all necessary clock signals for various modules. The crystal accuracy should be under
30ppm to ensure the best quality.
8.5. Thermal Considerations
To maintain a stable operating condition, the system designer should stay within maximum temperature
limits. The temperature of the chip case (center of top side) should not exceed 90°C in any condition.
8.6. Power-On Sequence
Generally, the power-on sequence should be as follows:
• Apply 3.3V, 1.0V, and 1.5V
• Wait for power supplies to be stable
• Reset operation completes
• System boots up
The RTD1186 integrates a Power-On-Reset (POR) circuit to ensure the chip powers up in a default state.
It monitors the status of 3.3V and 1.0V. The POR circuit reset will release after 220
crystal clock cycles
when both VDD and VCORE are stable.
Figure 5. POR Circuit Diagram
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The Power-On-Reset (POR) will assert a reset signal when the 3.3V or 1.0V fall below certain voltage
levels. Refer to Figure 6, the sequence of applying 3.3V and 1.0V is suggested to be 1.0V leads 3.3V.
1.5V is required to be stable before the end of the reset duration, that is, t2 > 0.
Figure 6. Power-On Sequence Timing Diagram
Table 5. POR Circuit Specification
Parameter Description TYP. Unit
3.3V_MIN Minimum Voltage to De-Assert POR 2.5 V
1.0V_MIN Minimum Voltage to De-Assert POR 0.8 V
3.3V_DROP Trigger Voltage to Assert POR 2.0 V
1.0V_DROP Trigger Voltage to Assert POR 0.75 V
tPOR POR Reset Time 220
Cycles
t1 Lead Time between 1.0V and 3.3V 2 mS
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9. DDR3 Controller Unit
The RTD1186 DDR3 Controller Unit (DCU) provides memory control signals required for external
DDR3 SDRAM access. With a 32-bit-wide DDR3 SDRAM, the DCU can access up to 2GB.
9.1. Features
• Supports up to 2GB
• Supports Spread Spectrum Clocking (SSC)
• 1.5V SSTL15 compatible I/O
9.2. DCU Block External Pin Description
Table 6. DCU Block External Pin Description
Pin Name IO Standard Type Description
DDR3_CK SSTL15 DO DDR3 Clock Output
DDR3_CK# SSTL15 DO DDR3 Inverse Clock Output
DDR3_CKE SSTL15 DO DDR3 Clock Enable Output
DDR3_ODT SSTL15 DO DDR3 On-Die-Termination
DDR3_CS# SSTL15 DO DDR3 Chip Select Output
DDR3_RAS# SSTL15 DO DDR3 Row Address Select Output
DDR3_CAS# SSTL15 DO DDR3 Column Address Select Output
DDR3_WE# SSTL15 DO DDR3 Write Enable Output
DDR3_RESET# SSTL15 DO DDR3 Reset
DDR3_LLDQS SSTL15 DB DDR3 DQ[7:0] Data Strobe
DDR3_LLDQS# SSTL15 DB DDR3 DQ[7:0] Data Strobe
DDR3_LUDQS SSTL15 DB DDR3 DQ[15:8] Data Strobe
DDR3_LUDQS# SSTL15 DB DDR3 DQ[15:8] Data Strobe
DDR3_ULDQS SSTL15 DB DDR3 DQ[23:16] Data Strobe
DDR3_ULDQS# SSTL15 DB DDR3 DQ[23:16] Data Strobe
DDR3_UUDQS SSTL15 DB DDR3 DQ[31:24] Data Strobe
DDR3_UUDQS# SSTL15 DB DDR3 DQ[31:24] Data Strobe
DDR3_LLDM SSTL15 DO DDR3 DQ[7:0] Data Mask
DDR3_LUDM SSTL15 DO DDR3 DQ[15:8] Data Mask
DDR3_ULDM SSTL15 DO DDR3 DQ[23:16] Data Mask
DDR3_UUDM SSTL15 DO DDR3 DQ[31:24] Data Mask
DDR3_A[15:0] SSTL15 DO DDR3 Address[15:0]
DDR3_BA[2:0] SSTL15 DO DDR3 Bank Address[2:0]
DDR3_DQ[31:0] SSTL15 DB DDR3 Data[31:0]
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9.3. SSTL15 Un-Terminated Output Load Example
Main Chip DDRIII
VDDQ
VREF
DVRI
1.5V
0.75V
0.75V
DZQ
240/F
240/F
ZQ
Figure 7. SSTL15 Un-Terminated Output Load Example
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10. Flash Controller
The flash controller supports serial NOR flash memory and 8-bit NAND type flash memory. Each type
could be configured as boot device.
10.1. Feature
• Serial NOR Flash
ƒ Supports up to 16MB
ƒ Supports dual I/O read
ƒ Compliant with MXIC protocol
• NAND Flash
ƒ Supports up to 8GB
ƒ Built-in SRAM buffer to improve performance
ƒ Built-in 6/12/24-bit ECC mechanism to enhance data reliability
ƒ Supports up to 2 flash chips with interleave accessing
10.2. Serial Flash Block External Pin Description
Table 7. Serial Flash Block External Pin Description
Pin Name IO Standard Type Description
SPI_CE# LVTTL DO Serial Flash Chip Select Output
SPI_SCK LVTTL DO Serial Flash Clock
SPI_SI/SIO0 LVTTL DB Serial Flash Data Input (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O read mode)
SPI_SO/SIO1 LVTTL DB Serial Flash Data Output (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O read mode)
10.3. NAND Flash Block External Pin Description
Table 8. NAND Flash Block External Pin Description
Pin Name IO Standard Type Description
NAND_CLE LVTTL DO NAND Flash Command Latch Enable
NAND_ALE LVTTL DO NAND Flash Address Latch Enable
NAND_RD# LVTTL DO NAND Flash Read Enable
NAND_WR# LVTTL DO NAND Flash Write Enable
NAND_RDY LVTTL DI NAND Flash Ready
NAND_CE[3:0]# LVTTL DO NAND Flash Chip Enable[3:0]
NAND_D[7:0] LVTTL DB NAND Flash Data[7:0]
