• SYSTEM featured Field-Programmable Gate Arrays
- SelectRAMTM
MEMORY: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -2 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight GLOBAL low-skew clock or signal distribution
networks
• System Performance beyond 80 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable OUTPUT slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
• Configured by Loading Binary File
- Unlimited re-programmability
• Read Back Capability
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 μm SRAM process for XC4000XL
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRingTM
I/O Interconnect for Better Fixed
Pinout Flexibility
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• Four Additional Address Bits in Master Parallel
Configuration Mode
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深圳斯普仑科技有限公司
Shenzhen Spring Technology Co.,Ltd
地址：深圳市福田区振兴西路101栋华匀大厦730室
Add：Rm 730, Huayun building, Zhenxing Rd, Futian district,Shenzhen City, Guangdong Province 518031
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