LOW SKEW 첨1, 첨2 CLOCK GENERATOR

GENERAL DESCRIPTION The ICS8701I is a low skew, ÷1, ÷2 Clock Generator. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series term

文件：123.09 Kbytes 页数：13 Pages

ICST

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator

FEATURES • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maxi

文件：865.7 Kbytes 页数：16 Pages

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瑞萨

丝印：ICS8701CYILF；Package：LQFP；Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

文件：341.61 Kbytes 页数：15 Pages

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瑞萨

丝印：ICS8701CYILF；Package：LQFP；Low Skew, ÷1, ÷2 Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Par

文件：341.61 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：ICS8701CYLF；Package：LQFP；Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • One LVCMOS/LVTTL clock input • Maximum output frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank s

文件：373.8 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：ICS8701CYLF；Package：LQFP；Low Skew, ÷1, ÷2 LVCMOS/LVTTL Clock Generator

FEATURES • Twenty LVCMOS outputs, 7Ω typical output impedance • One LVCMOS/LVTTL clock input • Maximum output frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank s

文件：373.8 Kbytes 页数：14 Pages

RENESAS

瑞萨

丝印：ICS87016AYLF；Package：LQFP；Low Skew LVCMOS/LVTTL Clock Generator

文件：271.26 Kbytes 页数：17 Pages

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