丝印：ICS1894K32L；Package：QFN；10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

Features • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant • MIIM (MDC/MDIO) management bus fo

文件：513.21 Kbytes 页数：51 Pages

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丝印：ICS1894K32L；Package：QFN；10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

Features • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant • MIIM (MDC/MDIO) management bus fo

文件：513.21 Kbytes 页数：51 Pages

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丝印：ICS1894K33L；Package：QFN；10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

Features • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant • MIIM (MDC/MDIO) management bus f

文件：554.76 Kbytes 页数：39 Pages

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丝印：ICS1894K33L；Package：QFN；10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

Features • Supports category 5 cables and above with attenuation in excess of 24dB at 100 MHz. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sub layers functions of IEEE standard. • 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant • MIIM (MDC/MDIO) management bus f

文件：554.76 Kbytes 页数：39 Pages

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丝印：ICS0252BI03L；Package：TQFP；VCXO Jitter Attenuator and FemtoClock™ Multiplier

FEATURES • Two LVCMOS/LVTTL outputs, 17Ω impedance Each output supports independent frequency selection at 25MHz, 62.5MHz, 125MHz, and 156.25MHz • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz in

文件：902.59 Kbytes 页数：25 Pages

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丝印：ICS0252BI03L；Package：TQFP；VCXO Jitter Attenuator and FemtoClock™ Multiplier

FEATURES • Two LVCMOS/LVTTL outputs, 17Ω impedance Each output supports independent frequency selection at 25MHz, 62.5MHz, 125MHz, and 156.25MHz • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz in

文件：902.59 Kbytes 页数：25 Pages

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丝印：ICS02015AIL；Package：VFQFN；FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

Features • Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz • Crystal input frequency: 25MHz • Maximum

文件：476.72 Kbytes 页数：20 Pages

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丝印：ICS02015AIL；Package：VFQFN；FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

Features • Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz • Crystal input frequency: 25MHz • Maximum

文件：476.72 Kbytes 页数：20 Pages

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丝印：ICS02015AIL；Package：VFQFN；FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

Features • Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz • Crystal input frequency: 25MHz • Maximum

文件：476.72 Kbytes 页数：20 Pages

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丝印：ICS02015AIL；Package：VFQFN；FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency

Features • Three banks of outputs: Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz or 50MHz Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz Bank C: three differential LVDS outputs at 125MHz Reference LVCMOS/LVTTL output at 25MHz • Crystal input frequency: 25MHz • Maximum

文件：476.72 Kbytes 页数：20 Pages

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