丝印：ICS2008BVLFT；Package：PLCC；SMPTE Time Code Receiver/Generator

Features • Meets SMPTE VITC Specifications • Meets SMPTE and EBU LTC Specifications • Time Code Burn-in Window – Programmable position, size and character attributes • LTC edge rate control – Conforms to EBU Tr and Tf Specifications • Internal and external sync sources – Genlock to video o

文件：733.66 Kbytes 页数：23 Pages

RENESAS

瑞萨

SMPTE Time Code Receiver/Generator

General Description The ICS2008B, SMPTE Time Code Receiver/Generator chip, is a VLSI device designed in a low power CMOS process. This device provides the timing coordination for Multimedia sight and sound events. Although it is aimed at a PC Multimedia environment, the ICS2008B is easily integra

文件：316 Kbytes 页数：21 Pages

ICST

丝印：2008BY-10LF；Package：TQFP；SMPTE Time Code Receiver/Generator

Features • Meets SMPTE VITC Specifications • Meets SMPTE and EBU LTC Specifications • Time Code Burn-in Window – Programmable position, size and character attributes • LTC edge rate control – Conforms to EBU Tr and Tf Specifications • Internal and external sync sources – Genlock to video o

文件：733.66 Kbytes 页数：23 Pages

RENESAS

瑞萨

丝印：2008BY-10LF；Package：TQFP；SMPTE Time Code Receiver/Generator

Features • Meets SMPTE VITC Specifications • Meets SMPTE and EBU LTC Specifications • Time Code Burn-in Window – Programmable position, size and character attributes • LTC edge rate control – Conforms to EBU Tr and Tf Specifications • Internal and external sync sources – Genlock to video o

文件：733.66 Kbytes 页数：23 Pages

RENESAS

瑞萨

CLOCK MULTIPLIER AND JITTER ATTENUAT

Features • Excellent jitter attenuation for telecom and video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation offers very low jitter and phase noise generation • Output clock is phase and frequency locked to the selected inp

文件：454.42 Kbytes 页数：13 Pages

RENESAS

瑞萨

LOW SKEW PCI/PCI-X BUFFER

Features • Packaged in 8-pin TSSOP (4.4 mm body) • Frequency range of 0 to 140 MHz • Less than 100 ps skew between outputs • Distribute one clock input to one bank of four outputs • Operating voltage of 3.3 V ±10 • Available in commercial and industrial temperature ranges

文件：284.64 Kbytes 页数：12 Pages

RENESAS

瑞萨

FEMTOCLOCKS??CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER

文件：844.84 Kbytes 页数：16 Pages

IDT

175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

文件：3.64768 Mbytes 页数：23 Pages

IDT

700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR

文件：3.11985 Mbytes 页数：23 Pages

IDT

FEMTOCLOCKS??VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

文件：300.84 Kbytes 页数：18 Pages

IDT