General Power SPDT Switch: DC~6 GHz

Hexawave

汉威电子

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 页数：4 Pages

ICST

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 页数：4 Pages

ICST

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 页数：4 Pages

ICST