256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

ELPIDA

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256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

ELPIDA

尔必达

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

ELPIDA

尔必达

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

ELPIDA

尔必达

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

ELPIDA

尔必达

256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 횞 16-bit 횞 4-bank/8-Mword 횞 8-bit 횞 4-bank/ 16-Mword 횞 4-bit 횞 4-bank

Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS)

文件：489.7 Kbytes 页数：65 Pages

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Inductive Cell Balancer IC with Balacing Curret Up to 2A

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丝印：GSYW；Package：DFN2X2-8L；Inductive Cell Balancer IC with Balacing Curret Up to 2A

文件：7.40108 Mbytes 页数：11 Pages

HMSEMI

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丝印：GIYW；Package：SOT23-6L；Inductive Cell Balancer IC with Balacing Curret Up to 2A

文件：7.40108 Mbytes 页数：11 Pages

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