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HEF4042B

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042BD

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042BF

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042BN

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042BP

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042BT

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件:60.89 Kbytes 页数:6 Pages

PHI

飞利浦

PHI

HEF4042B

Quadruple D-latch

恩XP

恩XP

HEF4042BD

Quadruple D-latch

恩XP

恩XP

详细参数

  • 型号:

    HEF4042B

  • 功能描述:

    1-Bit D-Type Latch

供应商型号品牌批号封装库存备注价格
PHI
2015+
CDIP16
19889
一级代理原装现货,特价热卖!
询价
A
24+
DIP-16
3
询价
PHI
8503
DIP-16/瓷封
950
原装现货海量库存欢迎咨询
询价
PHI
25+
DIP
2987
只售原装自家现货!诚信经营!欢迎来电!
询价
PHI
25+23+
DIP-16
35936
绝对原装正品全新进口深圳现货
询价
PHILI
18+
DIP
7608
全新原装现货,可出样品,可开增值税发票
询价
PHI
DIP
1211
优势库存
询价
PHSSEMICONDUCTOR
2447
NA
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
ST
1922+
DIP16
3689
原装进口现货库存专业工厂研究所配单供货
询价
PHI
24+
DIP-16
9600
原装现货,优势供应,支持实单!
询价
更多HEF4042B供应商 更新时间2025-11-24 16:36:00