CD4042

4位口型锁存器; • Supply voltage range:3V to 15V \n• Temperature range:-40℃ to +125℃\n• Packaging information: DIP16/SOP16/SSOP16/TSSOP16;

The CD4042 is a quad clocked “D” latch. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

CD4042B-MIL

CMOS 四路时钟控制“D”锁存器; • Clock polarity control\n• Q and Q\\ outputs\n• Common Clock\n• Low power TTL compatible\n• Standardized, symmetrical output characteristics\n• 100% tested for quiescent current at 20 V\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• 5-V, 10-V, and 15-V parametric ratings\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n• Applications: \n• Buffer storage\n• Holding register\n• General digital logic\n \n Data sheet acquired from Harris Semiconductor;

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.\n\n Information present at the data input is transferred to outputs Q and Q\\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.\n\n The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4042BMS

CMOS Quad D Latch, Clocked;

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

CD4042BMS

CMOS Quad Clocked “D” Latch

Description CD4042BMStypescontainfourlatchcircuits,eachstrobedbyacommonclock.Complementarybufferedoutputsareavailablefromeachcircuit.Theimpedanceofthen-andp-channeloutputdevicesisbalancedandalloutputsareelectricallyidentical. Applications •BufferSt

CD4042A

CMOS Quad Clocked D Latch

CD4042B

CMOS Quad Clocked D Latch

CD4042B

CMOS Quad Clocked D Latch

CD4042B_15

CMOS Quad Clocked D Latch

CD4042BC

Quad Clocked D Latch

CD4042BD

CMOS Quad Clocked D Latch