CMOS Quad Clocked “D” Latch

Description CD4042BMS types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p- channel output devices is balanced and all outputs are electrically identical. Applications • Buffer St

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INTERSIL

CMOS Quad D Latch, Clocked

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Renesas

瑞萨

QUAD CLOCKED D LATCH

Description The HCC4000B series is composed of close to 80 monolithic types built with Metal Oxide Complementary technology. It provides Designers with high voltage noise tolerant complete Logic series. It radiation hardness and immunity to Heavy Ions make this series to be usable in the

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STMICROELECTRONICS

意法半导体

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件：60.89 Kbytes 页数：6 Pages

PHI

PHI

Quadruple D-latch

DESCRIPTION The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the sam

文件：60.89 Kbytes 页数：6 Pages

PHI

PHI