5-stage Johnson counter

DESCRIPTION The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The

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PHI

PHI

5-stage Johnson decade counter

General description The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset in

文件：103.33 Kbytes 页数：16 Pages

恩XP

5-stage Johnson counter

DESCRIPTION The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The

文件：99.22 Kbytes 页数：8 Pages

PHI

PHI

RF & MICROWAVE TRANSISTORS 806-960 MHz CELLULAR BASE STATIONS

DESCRIPTION The SD4017 is a gold metallized epitaxial silicon NPN planar transistor using diffused emitter ballast resistors for high linearity class AB operation for cellular base station applications. ■ GOLD METALLIZATION ■ DIFFUSED EMITTER BALLASTING ■ INTERNAL INPUT MATCHING ■ DESIGNED FO

文件：87.15 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体

DECADE COUNTER/DIVIDER

TC4017BP/BF is decimal Johnson counter consisting of 5 stage D-type flip-flop equipped with the decoder to convert the output to decimal. Depending on the number of count pulses fed to CLOCK or CLOCK INHIBIT one output among 10 output lines “Q0” through “Q9” becomes “H” level. The counter advances

文件：277.36 Kbytes 页数：6 Pages

TOSHIBA

东芝