3-Line-to-8-Line Decoders / Demultiplexers

The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external

文件：100.23 Kbytes 页数：8 Pages

RENESAS

瑞萨

3-Line-to-8-Line Decoders / Demultiplexers

文件：120.84 Kbytes 页数：10 Pages

RENESAS

瑞萨

General-Purpose Logics-HD74LS Series

Renesas

瑞萨

3-Line-to-8-Line Decoders / Demultiplexers

The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external

文件：100.23 Kbytes 页数：8 Pages

RENESAS

瑞萨

3-Line-to-8-Line Decoders / Demultiplexers

文件：120.84 Kbytes 页数：10 Pages

RENESAS

瑞萨

3-to-8-Line Decoder/Demultiplexer

3-to-8-Line Decoder/Demultiplexer This schottky-clamped TTL MSI circuit is designed to be used in high-performance memory-decording or data-routing applications requiring very short propagation delay time. In high-performance memory systems this decode can be used to minimize the effects of syste

文件：153.58 Kbytes 页数：3 Pages

INTEGRAL

Integral Corp.