Triple 3-input NAND Gates

Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：39.74 Kbytes 页数：7 Pages

HitachiHitachi Semiconductor

日立日立公司

Triple 3-input NAND Gates

Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：84.24 Kbytes 页数：7 Pages

RENESAS

瑞萨

Triple 3-input NAND Gates

HITACHI

日立

Standard IC>General-Purpose Logics>HD74HC Series

Renesas

瑞萨

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

文件：106.53 Kbytes 页数：8 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Clear)

Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

文件：57.93 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

日立日立公司

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

文件：106.53 Kbytes 页数：8 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

文件：106.53 Kbytes 页数：8 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

文件：106.53 Kbytes 页数：8 Pages

RENESAS

瑞萨

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

文件：87.37 Kbytes 页数：7 Pages

RENESAS

瑞萨