Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

文件：55.14 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

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Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

文件：87.37 Kbytes 页数：7 Pages

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Standard IC>General-Purpose Logics>HD74HC Series

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Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Features • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V

文件：87.37 Kbytes 页数：7 Pages

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Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description\nThis flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 10 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C);

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