HD74HC108RP中文资料Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)数据手册Renesas规格书

描述 Description

This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse.

特性 Features

• High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)