3.3-V 20-bit Flip Flops with 3-state Outputs

Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output curren

文件：251.21 Kbytes 页数：12 Pages

RENESAS

瑞萨

3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs

Description The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

文件：51.31 Kbytes 页数：12 Pages

HitachiHitachi Semiconductor

日立日立公司

3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs

Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V, T

文件：56.93 Kbytes 页数：12 Pages

HitachiHitachi Semiconductor

日立日立公司

18-bit Buffers / Drivers with 3-state Outputs

Description The HD74ALVCH162825 can be used as two 9-bit buffers or one 18-bit buffer. It provides true data. The 3-state control gate is a 2-input AND gate with active low inputs so that if either output enable (OE1 or OE2) input is high, all nine affected outputs are in the high impedance state

文件：55.6 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

日立日立公司

20-bit Buffers / Drivers with 3-state Outputs

Description The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is h

文件：48.12 Kbytes 页数：10 Pages

HitachiHitachi Semiconductor

日立日立公司

20-bit Buffers / Drivers with 3-state Outputs

Description The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is h

文件：2.4575 Mbytes 页数：10 Pages

RENESAS

瑞萨

1-bit to 2-bit Address Driver with 3-state Outputs

Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V VCC operation. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of t

文件：2.28183 Mbytes 页数：11 Pages

RENESAS

瑞萨

1-bit to 2-bit Address Driver with 3-state Outputs

Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V VCC operation. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of

文件：55.25 Kbytes 页数：11 Pages

HitachiHitachi Semiconductor

日立日立公司

1-bit 4-bit Address Register / Driver with 3-state Outputs

Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce

文件：61.53 Kbytes 页数：13 Pages

HitachiHitachi Semiconductor

日立日立公司

1-bit 4-bit Address Register / Driver with 3-state Outputs

Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce

文件：2.95551 Mbytes 页数：13 Pages

RENESAS

瑞萨