3.3-V 20-bit Flip Flops with 3-state Outputs

Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output curren

文件：52.33 Kbytes 页数：12 Pages

HITACHIHitachi Semiconductor

日立日立公司

3.3-V 20-bit Flip Flops with 3-state Outputs

Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output curren

文件：251.21 Kbytes 页数：12 Pages

RENESAS

瑞萨

Standard IC>General-Purpose Logics>HD74ALVC Series

Renesas

瑞萨

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the

文件：111.76 Kbytes 页数：6 Pages

IDT

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the

文件：111.76 Kbytes 页数：6 Pages

IDT

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the

文件：111.76 Kbytes 页数：6 Pages

IDT