Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

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Altera

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Cyclone Series Device Thermal Resistance

Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons

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Altera

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1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store conf

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Package Information Datasheet for Mature Altera Devices

文件：2.063429 Mbytes 页数：182 Pages

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Enhanced Configuration (EPC) Devices Datasheet

文件：633.77 Kbytes 页数：36 Pages

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Package Information Datasheet for Mature Altera Devices

文件：2.06334 Mbytes 页数：182 Pages

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This datasheet describes enhanced configuration (EPC) devices

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Cyclone Device Handbook, Volume 1

文件：5.60108 Mbytes 页数：385 Pages

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Cyclone FPGA Family

文件：1.14233 Mbytes 页数：94 Pages

Altera

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Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 页数：104 Pages

Altera

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