3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link??5 MHz

文件：184.75 Kbytes 页数：9 Pages

NSCNational Semiconductor (TI)

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丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

丝印：DS90CF363BMT；Package：TSSOP；3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

1FEATURES 2• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5&#

文件：668.13 Kbytes 页数：19 Pages

TI

德州仪器

+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link—65 MHz

General Description\nThe DS90CF363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of inp 20 to 65 MHz shift clock support\nSingle 3.3V supply\nChipset (Tx + Rx) power consumption<250 mW (typ)\nPower-down mode (<0.5 mW total)\nSingle pixel per clock XGA (1024x768) ready\nSupports VGA, SVGA, XGA and higher addressability.\nUp to 170 Megabytes/sec bandwidth\nUp to 1.3 Gbps throughput\nNarr;

TI

德州仪器