DS90CF363数据手册集成电路（IC）的专用规格书PDF

描述 Description

General Description
The DS90CF363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 170 Mbytes/sec.

特性 Features

20 to 65 MHz shift clock support
Single 3.3V supply
Chipset (Tx + Rx) power consumption<250 mW (typ)
Power-down mode (<0.5 mW total)
Single pixel per clock XGA (1024x768) ready
Supports VGA, SVGA, XGA and higher addressability.
Up to 170 Megabytes/sec bandwidth
Up to 1.3 Gbps throughput
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 48-lead TSSOP package
Falling edge data strobe Transmitter
Compatible with TIA/EIA-644 LVDS standard
ESD rating7kV
Operating Temperature: −40˚C to +85˚C