DS90C383AMTD数据手册TI中文资料规格书

描述 Description

General Description
The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel.
Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF384) without any translation logic.

特性 Features

■ 20 to 65 MHz shift clock support
■ Rejects ± 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC)
■ Best–in–Class Set & Hold Times on TxINPUTs
■ Tx power consumption <130 mW (typ) @65MHz Grayscale
■ 50% Less Power Dissipation than BiCMOS Alternatives
■ Tx Power-down mode <200µW (max)
■ ESD rating 7 kV (HBM), 500V (EIAJ)
■ Supports VGA, SVGA, XGA and Dual Pixel SXGA.
■ Narrow bus reduces cable size and cost
■ Up to 1.8 Gbps throughput
■ Up to 227 Megabytes/sec bandwidth
■ 345 mV (typ) swing LVDS devices for low EMI
■ PLL requires no external components
■ Compatible with TIA/EIA-644 LVDS standard
■ Low profile 56-lead TSSOP package
■ Improved replacement for:
   SN75LVDS83 — DS90C383A
   SN75LVDS81 — DS90CF383A