5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 解串器

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between paral • 5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions\n• User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable\n• User-Selectable Clock Edge for Parallel Data on Both Transmitte;

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德州仪器

5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

文件：992.38 Kbytes 页数：31 Pages

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德州仪器

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德州仪器

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