3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：344.12 Kbytes 页数：20 Pages

NSC

国半

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

丝印：DS90C383MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit

文件：811.57 Kbytes 页数：30 Pages

TI

德州仪器

3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

文件：410.45 Kbytes 页数：22 Pages

TI

德州仪器