DRA829 Jacinto??Processors Silicon Revisions 1.0 and 1.1

文件：7.12776 Mbytes 页数：319 Pages

TI

德州仪器

DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

丝印：DRA829JMTGBALF942；Package：FCBGA；DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

丝印：DRA829JMTGBALFQ1942；Package：FCBGA；DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

丝印：DRA829JMTGCALF942；Package：FCBGA；DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

丝印：DRA829JMTGCALFQ1942；Package：FCBGA；DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器

丝印：DRA829VMTGBALF942；Package：FCBGA；DRA829 Processors

1 Features Processor cores: • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core • Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache,

文件：6.31075 Mbytes 页数：328 Pages

TI

德州仪器