Octal D-Type Transparent Latch with 3-STATE Outputs

General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly

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Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

文件：48.06 Kbytes 页数：4 Pages

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Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

文件：48.06 Kbytes 页数：4 Pages

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Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

文件：48.06 Kbytes 页数：4 Pages

FAIRCHILD

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Inverting Octal Bus Transceiver

General Description This inverting octal bus transceiver is designed for asynchronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G

文件：48.06 Kbytes 页数：4 Pages

FAIRCHILD

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Octal Bus Transceivers

General Description These octal bus transceivers are designed for asynchronous two-way communication between data busses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can

文件：47.84 Kbytes 页数：4 Pages

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Octal Bus Transceivers

General Description These octal bus transceivers are designed for asynchronous two-way communication between data busses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can

文件：47.84 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Octal Bus Transceivers

General Description These octal bus transceivers are designed for asynchronous two-way communication between data busses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can

文件：47.84 Kbytes 页数：4 Pages

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Octal 3-STATE Bus Transceiver and Register

General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over ful

文件：56.16 Kbytes 页数：6 Pages

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Octal 3-STATE Bus Transceiver and Register

General Description This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over ful

文件：56.16 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体