144-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：894.86 Kbytes 页数：33 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support

文件：867.5 Kbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

文件：894.86 Kbytes 页数：33 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support

文件：867.5 Kbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

文件：753 Kbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

文件：753 Kbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

文件：753 Kbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes 页数：32 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司