CDCDB2000NPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB803ERSLR

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCDB803ERSLT

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCDB803RSLR

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCDB803RSLT

Marking：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1Features •8LP-HCSLoutputswithprogrammableintegrated 85-Ω(default)or100-Ωdifferentialoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterPCIEGen6filter:20fs, RMS(maximum) •AdditivephasejitterafterPCIEGen5filter:25fs, RMS(

CDCF2509PWR

Marking：CDCF2509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2509AasaReplacementfor thisDevice DesignedtoMeetPC133SDRAM RegisteredDIMMSpecificationRev.0.9 SpreadSpectrumClockCompatible OperatingFrequency25MHzto140MHz StaticPhaseErrorDistributionat66MHzto 133MHzis±125ps Jitter(cyc−cyc)at66MHzto133MHzI

CDCF2509PWR.B

Marking：CDCF2509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2509AasaReplacementfor thisDevice DesignedtoMeetPC133SDRAM RegisteredDIMMSpecificationRev.0.9 SpreadSpectrumClockCompatible OperatingFrequency25MHzto140MHz StaticPhaseErrorDistributionat66MHzto 133MHzis±125ps Jitter(cyc−cyc)at66MHzto133MHzI

CDCLVP111HFG/EM

Marking：CDCLVP111HFG/EM；Package：CFP；CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features •DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL •FullyCompatibleWithLVECLandLVPECL •SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V •SelectableClockInputThroughCLK_SEL •Low-OutputSkew(Typical15ps)forClock- Distribution

CDCLVP111HFGSLASHEM

Marking：CDCLVP111HFG/EM；Package：CFP；CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features •DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL •FullyCompatibleWithLVECLandLVPECL •SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V •SelectableClockInputThroughCLK_SEL •Low-OutputSkew(Typical15ps)forClock- Distribution