CDC2351DW.B

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWR

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWR.B

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC2351DWRG4

Marking：CDC2351；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications Operatesat3.3-VVCC LVTTL-CompatibleInputsandOutputs SupportsMixed-ModeSignalOperation (5-VInputandOutputVoltagesWith3.3-V VCC) DistributesOneClockInputtoTenOutputs OutputsHaveIn

CDC319DB

Marking：CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed,Low-Skew1-to-10ClockBuffer forSDRAM(SynchronousDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoTwoUnbufferedSDRAM DIMMs(DualInlineMemoryModules) I2CSerialInterfaceProvidesIndividual Ena

CDC319DB.B

Marking：CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed,Low-Skew1-to-10ClockBuffer forSDRAM(SynchronousDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoTwoUnbufferedSDRAM DIMMs(DualInlineMemoryModules) I2CSerialInterfaceProvidesIndividual Ena

CDC319DBR

Marking：CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed,Low-Skew1-to-10ClockBuffer forSDRAM(SynchronousDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoTwoUnbufferedSDRAM DIMMs(DualInlineMemoryModules) I2CSerialInterfaceProvidesIndividual Ena

CDC319DBR.B

Marking：CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed,Low-Skew1-to-10ClockBuffer forSDRAM(SynchronousDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoTwoUnbufferedSDRAM DIMMs(DualInlineMemoryModules) I2CSerialInterfaceProvidesIndividual Ena

CDC328AD

Marking：CDC328A；Package：SOIC；1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY

LowOutputSkewforClock-Distribution andClock-GenerationApplications TTL-CompatibleInputsandOutputs DistributesOneClockInputtoSixClock Outputs PolarityControlSelectsTrueor ComplementaryOutputs DistributedVCCandGNDPinsReduce SwitchingNoise High-DriveOutputs(−48-mA

CDC328AD.B

Marking：CDC328A；Package：SOIC；1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY

LowOutputSkewforClock-Distribution andClock-GenerationApplications TTL-CompatibleInputsandOutputs DistributesOneClockInputtoSixClock Outputs PolarityControlSelectsTrueor ComplementaryOutputs DistributedVCCandGNDPinsReduce SwitchingNoise High-DriveOutputs(−48-mA