CDC351IDW.Z

Marking：CDC351-I；Package：SOIC；1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·LowOutputSkew,LowPulseSkewfor Clock-DistributionandClock-Generation Applications ·Operatesat3.3-VVCC ·LVTTL-CompatibleInputsandOutputs ·SupportsMixed-ModeSignalOperation(5-V InputandOutputVoltagesWith3.3-VVCC) ·DistributesOneClockInputtoTenOutpu

CDC536DB

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDC536DB.B

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDC536DBG4

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDC536DBR

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDC536DBR.B

Marking：CDC536；Package：SSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES ·Low-OutputSkewforClock-Distributionand Clock-GenerationApplications ·Operatesat3.3-VVCC ·DistributesOneClockInputtoSixOutputs ·OneSelectInputConfiguresThreeOutputsto OperateatOne-HalforDoubletheInput Frequency ·NoExternalRCNetworkRequired ·Ext

CDCDB2000ENPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000ENPPT

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter:

CDCDB2000NPPR

Marking：CDCDB2000；Package：TLGA；CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5

1Features •20LP-HCSLoutputswithintegrated85-Ωoutput terminations •8hardwareoutputenable(OE#)controls •AdditivephasejitterafterDB2000QLfilter: