丝印：CD4517BE；Package：PDIP；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

丝印：CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted

文件：116.61 Kbytes 页数：9 Pages

INTERSIL

CMOS Dual Up Counters

Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-g

文件：112.68 Kbytes 页数：10 Pages

INTERSIL

CMOS Dual Up-Counters

Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat

文件：986.41 Kbytes 页数：22 Pages

TI

德州仪器

丝印：CD4518BE；Package：PDIP；CMOS Dual Up-Counters

Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat

文件：986.41 Kbytes 页数：22 Pages

TI

德州仪器

丝印：CD4518BE；Package：PDIP；CMOS Dual Up-Counters

Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat

文件：986.41 Kbytes 页数：22 Pages

TI

德州仪器

丝印：CD4518BE；Package：PDIP；CMOS Dual Up-Counters

Features: Medium-speed operation — 6-MHz typical clock frequency st 10 V, = Positive- or negative-edge triggering m Synchronous internal carry propagation . 100% tested for quiescent current at 20 V & Maximum input current of 1 uA at 18 V ‘over full package-temperature range; 100 nAat

文件：986.41 Kbytes 页数：22 Pages

TI

德州仪器