丝印：CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 页数：11 Pages

TI

德州仪器

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes 页数：9 Pages

TI

德州仪器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes 页数：9 Pages

TI

德州仪器