CD4518B

CMOS双路BCD（十进制）加法计数器;

CD4518B是双十进制同步加法计数器，CD4520B是双四位二进制同步加法计数器，二者均是由两个相同的、内置同步4级计数器。每级计数器均由D型触发器构成。由于具有可互换的CLOCK和ENABLE输入端口，CD4518B/4520B既可由上升沿触发也可由下降沿时触发。对于单个操作来说，ENALBE输入用来维持高电平，并在每个CLOCK正向变化时更新计数器。计数器在RESET为高电平时清零。计数器实现在行波模式下的级连，即一个计数器Q4连接到后继计数器的使能输入端，并且后继计数器的CLOCK输入端保持低电平。\n\nCD4518B和CD4520B的封装形式有DIP16和SOP16。

CD4518B

CMOS 双路 BCD 加法计数器; • Medium-speed operation -    6-MHz typical clock frequency at 10 V\n• Positive- or negative-edge triggering\n• Synchronous internal carry propagation\n• 100% tested for quiescent current at 20 V\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise margin (over full package-temperature range): \n• 1 V at VDD = 5 V\n• 2 V at VDD = 10 V\n• 2.5 V at VDD = 15 V\n \n• 5-V, 10-V, and 15-V parametric ratings\n• Standardized, symmetrical output characteristics\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n• Applications \n• Multistage synchronous counting\n• Multistage ripple counting\n• Frequency dividers\n \n Data sheet acquired from Harris Semiconductor.;

CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.\n\n The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.\n\n The CD4518B and CD4520B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4518B

CD4000系列 逻辑芯片;

CD4518B

CMOS DUAL UP-COUNTERS

CD4518B

CMOS Dual Up-Counters

CD4518B

Cmos Dual Up-Counters

CD4518BMS

CMOS Dual Up Counters

Description CD4518BMSDualBCDUpCounterandCD4520BMSDualBinaryUpCountereachconsistoftwoidentical,internallysynchronous4-stagecounters.ThecounterstagesareD-typeflip-flopshavinginterchangeableCLOCKandENABLElinesforincrementingoneitherthepositive-goingornegative-g

CD4518B_16

Cmos Dual Up-Counters

CD4518BE

CMOS DUAL UP-COUNTERS

CD4518BE

CMOS Dual Up-Counters