丝印：CD4085BM；Package：SOIC；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BM；Package：SOIC；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

文件：78.58 Kbytes 页数：9 Pages

INTERSIL

丝印：CM085B；Package：TSSOP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CM085B；Package：TSSOP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BF3A；Package：CDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器