CMOS AND Gate

Description CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-I

文件：115.73 Kbytes 页数：10 Pages

INTERSIL

CMOS AND Gate

Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate (No longer available or supported) • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate (No longer available or supported) • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V • 100 T

文件：391.32 Kbytes 页数：11 Pages

RENESAS

瑞萨

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

文件：78.58 Kbytes 页数：9 Pages

INTERSIL

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BE；Package：PDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BE；Package：PDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BF；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BF；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BF3A；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器

丝印：CD4085BF3A；Package：CDIP；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

文件：938.91 Kbytes 页数：20 Pages

TI

德州仪器