丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

丝印：CD4086BE；Package：PDIP；CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 页数：17 Pages

TI

德州仪器

CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 页数：12 Pages

TI

德州仪器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

文件：828.89 Kbytes 页数：13 Pages

TI

德州仪器