CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

文件：94.49 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

文件：94.49 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

文件：94.49 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

文件：94.49 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器