丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BM；Package：SOIC；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029B；Package：SOP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

CMOS Presettable Up/Down Counter

Description\nCD4029BMS consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. • High-Voltage Type (20V Rating)\n• Medium Speed Operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V\n• Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times\n• “Preset Enable” and Individual “Jam” Inputs Provided\n;

Renesas

瑞萨

Presettable Binary/Decade Up/Down Counter

General Description\nThe CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counter co ■Wide supply voltage range: 3V to 15V\n■High noise immunity: 0.45 VDD(typ.)\n■Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS\n■Parallel jam inputs\n■Binary or BCD decade up/down counting;

ONSEMI

安森美半导体

CMOS PRESETTABLE UP/DOWN COUNTER

TI

德州仪器

CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器