Presettable Binary/Decade Up/Down Counter

General Description The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical “1”, the counter counts in binary, other wise it counts in decade. Similarly, the counte

文件：94.49 Kbytes 页数：8 Pages

Fairchild

仙童半导体

CMOS Presettable Up/Down Counter

Description CD4029BMS consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. Features • High-Voltage Type (20V Rating) • Medium Speed Operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V • Multi-Package Paralle

文件：124.65 Kbytes 页数：11 Pages

Intersil

CMOS Presettable Up/Down Counter

Features High-Voltage Type (20V Rating) Medium Speed Operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times “Preset Enable” and Individual “Jam” Inputs Pro

文件：156.19 Kbytes 页数：11 Pages

SYC

Presettable Binary/Decade Up/Down Counter

文件：164.2 Kbytes 页数：8 Pages

NSC

国半

Presettable Binary/Decade Up/Down Counter

文件：164.21 Kbytes 页数：8 Pages

NSC

国半

CMOS PRESETTABLE UP/DOWN COUNTER

文件：302.49 Kbytes 页数：7 Pages

TI

德州仪器

CMOS PRESETTABLE UP/DOWN COUNTER

文件：1.03602 Mbytes 页数：18 Pages

TI

德州仪器

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BE；Package：PDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：CD4029BF；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器